CSE 140 Syllabus

Textbooks

Online Required Textbook: Digital Design by F. Vahid

  • 1.Sign up at learn.zybooks.com
  • 2.Enter zyBook code UCSDCSE140ChengSpring2019.
  • 3.Use an email address that ends with @ucsd.edu,
  • 4. enter Section A or B according to class enrollment,
  • 5. Subscription cost $50.00.

    • Students are required to have an account in zyBooks and to complete assigned exercises at a due time.

    It is important that you use the SAME username for both TED and ZyBooks. Here are the instruction on how to change the subscription details Any of the students can update their own subscription details from within the ZyBook, simply click on the action menu in the top right corner and select 'Show subscription'. From there you may update your subscription information.

    Recommended Textbooks and References: (reserved at Library)


    Grading

    Course Policy

    Schedule

    Week Lecture Homework zyBook Weekly Activities
    1 Course Overview - The digital abstraction and basic logic gates.
    Lecture 1 [pptx file] [ pdf file]     		zyBook Chapter 1 due Tu 4/9/19@2:00pm
    Combinational Logic: 1. scope; 2. Boolean algebra; 3. switching functions, logic diagrams, truth table; 4. handy tools: DeMorgan's, consensus, Shannon's expansion; 5. combinational circuits: POS and SOP canonical forms.
    Lecture 2 [pptx file] [pdf file]     		Homework 1, latex file due Monday 4/15/19@11:59pm
    2 Combinational Circuits: Logic minimization with 2-, multivariable- K-maps.
    Lecture 3 [pptx file] [pdf file]     		Homework 2, latex file due Monday 4/22/19@11:59pm zyBook Chapter 2 due Tu 4/16/19@2:00pm
    3 K-Maps (essential and non-essential prime implicants)
    Lecture 4 [pptx file] [pdf file]     		zyBook Chapter 4.1-4.3 due Tu 4/23/19@2:00pm
    K-Maps (essential and non-essential prime implicates) K-map to product of sum minimization K-Maps in higher dimensions
    Lecture 5 [pptx file] [pdf file]
    Universal set, XOR, NAND, NOR gates, and block diagram transfers
    Lecture 6 [pptx file] [pdf file]
    4 Sequential Networks: Introduction and memory components
    Lecture 7 [pptx file] [pdf file]     		zyBook Chapter 3.1-3.4 due Tu 4/30/19@2:00pm
    5 Sequential Networks: Specification, analysis and implementation
    Lecture 8 [pptx file] [pdf file]     		Homework 3, latex file due Monday 5/6/19@11:59pm zyBook Chapter 3.5-3.8 due Tu 5/7/19@2:00pm
    6 Sequential Networks: Timing and Retiming
    Lecture 10 [pptx file] [pdf file] Standard Modules:
    Decoders Lecture 11 [pptx file] [pdf file]
    Mutiplexers Lecture 12 [pptx file] [pdf file]     		Homework 4, latex file, Q1.eps for figure 1, Q2.eps for figure 2 due Monday 5/13/19@11:59pm. For midterm 2 exam, check samples and rubrics from CK's website. zyBook Chapter 3.9-3.12 due Tu 5/14/19@2:00pm
    7 Standard Modules:
    Adders and et al. Lecture 14 [pdf file] [pptx file].     		zyBook Chapters 4.4-4.6, 6.1-6.3 due Tu 5/21/19@2:00pm
    8 System Designs: Introduction and Implementation
    Lecture 16 [pptx file] [pdf file] [Chapter_9_Lang: Download from Piazza]
    Lecture 17 [pptx file] [pdf file]     		Homework 5, latex file, Ref 1 due Monday 6/3/19@11:59pm zyBook Chapters 6.4-6.11, 5.1-5.9 due Tu 5/28/19@2:00pm
    9 Standard Modules:
    Sequential modules Lecture 15 [pdf file] [pptx file].
    Floating point processes Lecture 19 [pdf file] [ppt file].     		zyBook Chapter 9.1-9.13 due Tu 6/4/19@2:00pm
    10
    System designs Lecture 18 [pdf file] [pptx file].
    Final Review     		Final Exam examples and rubrics check CK's website, e.g. http://cseweb.ucsd.edu/classes/sp18/cse140-a/discussions.html.
    Final subject coverage: lectures 14, 15, 16, 17, 19: standard modules (adders etc.), sequential modules, system designs, floating point processes.
    Exercise on sequential adders, counters and floating point processes pdf file, latex file, Reference pdf file.     		No zyBook requirement in W10