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\begin{document}
\title{CSE140 - HW \#4}
\author{Due Mon. 5/13/2019 by 11:59PM}
\date{}
\maketitle

\noindent
{\bf For the first two problems, we analyze the timing of sequential machines
to practice the concept of clock period, skew and retiming.
For the rest three problems, we practice the usage of standard interconnect
components.} \\

\noindent
1. Given the circuit in Figure~\ref{fig:XORs}, each two-input XOR gate has a
propagation delay of 60 ps and a contamination delay of 40 ps.  Each
flip-flop has a setup time of 60 ps, a hold time of 20 ps, a clock-to-Q
propagation delay of 70 ps, and a clock-to-Q contamination delay of 50 ps.

\noindent
(a) If there is no clock skew, what is the maximum operating frequency of
the circuit?

\noindent
(b) How much clock skew can the circuit tolerate before it might experience
a hold time violation?

\begin{figure}[ht!]
\centering
\includegraphics[width=\textwidth]{Q1.eps}
\caption{a sequential circuit with 11 Flip-Flops and 7 XOR gates}
\label{fig:XORs}
\end{figure}

\newpage
\noindent
2. A 16-input priority encoder can be built with four 4-input priority encoders such that the $E_o$ output of the first encoder is connected to the $E$ input of second encoder, the $E_o$ output of the second encoder is connected to the $E$ input of third encoder and so on as shown in
Figure~\ref{fig:adder}. The priority encoder has input and output registers and must complete its operation in one clock cycle. Each 4-input priority encoder has the following propagation delays: 20 ps from $E$ to $E_o$ or to $G_s$, 25 ps from $E$ to $Y_k$ and from $I_k$ to $G_S$, and 30 ps from $I_i$ to either $E_o$ or $Y_j$. Each 4-input priority encoder has the following contamination delays: 10 ps from $E$ to $E_o$ or to $G_s$, 15 ps from $E$ to $Y_k$ and from $I_k$ to $G_S$, and 20 ps from $I_i$ to either $E_o$ or $Y_j$. Each flip-flop has a setup time of 30 ps, a hold time of 10 ps, a clock-to-Q propagation delay of 35 ps, and a clock-to-Q contamination delay of 25 ps.

\noindent
(a) If there is no clock skew, what is the maximum operating frequency of
the circuit?

\noindent
(b) If there is retiming using designated skew, what is the maximum operating
frequency of the circuit?

\begin{figure}[h!]
\centering
\includegraphics[width=0.75\textwidth]{Q2.eps}
\caption{A 16-input priority encoder.}
\label{fig:adder}
\end{figure}

\newpage
\noindent
3. (Decoders) Given three four-input Boolean functions

\indent
$f_1 (a,b,c,d) = \sum m(3,4,6,10,13) + \sum d(1,2,8)$,

\indent
$f_2 (a,b,c,d) = \sum m(1,5,7,14) + \sum d(2,9,10)$,

\indent
$f_3 (a,b,c,d) = \sum m(2,8,9,15) + \sum d(10,12,14)$.

\noindent
3.1. Implement the functions using a minimal network of 4:16 decoders and
OR gates.

\noindent
3.2. Implement the functions using a minimal network of 3:8 decoders and
OR gates.

\noindent
3.3. Implement the functions using a minimal network of 2:4 decoders and
OR gates.
\\

\noindent
4. (Multiplexers) Assume a dual-railed system, where you have access to any
variable and its complement.
Implement the following four-input Boolean function as indicated in each
of the following subproblems.

\indent
$f(a,b,c,d) = \sum m(2,4,5,7,10,14,15) + \sum d(0,1,6,8,12)$.

\noindent
4.1. Implement the function using a minimal network of 8:1 multiplexers.

\noindent
4.2. Implement the function using a minimal network of 4:1 multiplexers.

\noindent
4.3. Implement the function using a minimal network of 2:1 multiplexers.
\\

\noindent
5. Assume a dual-railed system, where you have access to any variable and
its complement. Given a four-input Boolean function

\indent
$f(a,b,c,d) = \sum m(0,2,4,5,7,9,12) + \sum d(11,14)$.

\noindent
5.1. Implement the function using a minimal network of 2:4 decoders and
OR gates.

\noindent
5.2. Implement the function using a minimal network of 4:1 multiplexers.

\noindent
5.3. Implement the function using a minimal network of 2:1 multiplexers.

\end{document}