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\title{CSE140 - HW \#3}
\author{Due Monday May 6, 11:59PM }
\date{}
\maketitle

\section*{Introduction}
The purpose of this assignment is to get a better understanding of basic memory elements
and the design of sequential circuits.
In the first problem, we search and compare the memory devices.
For the second problem, we learn to analyze circuits with feedback loops.
In the third problem we draw a timing diagram for D-latch and D-flip-flop.
In the fourth problem, we translate a pattern recognizer into state diagrams and state tables.
Finally, in the fifth problem, we synthesize a sequential circuit.

\section{Memory Devices}

\noindent
Use a table to list and compare the cost and performance of ten different memory devices
(hint: feel free to search available references).

\section{Latch}
\noindent
(1). Given a SR latch of NOR gates, replace the two NOR gates with two NAND gates. 
Write the state table, state diagram and the characteristic expression of the revised
circuit (hint: follow the steps in slides 17, 18, 20 and 26 of lecture 7).

\noindent
(2). Given a SR latch of NOR gates, replace the NOR gates at the bottom (slide 17 of lecture 7)
with one NAND gate. Analyze the circuit.

\section{Timing Diagram of Latch and Flip-Flop}

\noindent
Timing Diagram of Latch and Flip-Flop:
Given the input waveforms shown below, sketch the output D-Latch of the latch and 
the output D-FF of the flip-flop.

\begin{figure}[ht!]
\label{fig: fig1}
\centering
\includegraphics[width=1\textwidth]{p3wave.png}
\end{figure}

\newpage
\section{Pattern Recognizer}

\noindent
A sequential network has one binary input $x(t)$ and
one binary output $y(t)$. The network produces $y=1$, whenever input pattern
$x(t-3,t)$= 1101 or 1011. Otherwise, the output $y=0$.

\indent
(i) Draw the state diagram.

\indent
(ii) Write the state table.

\section{Sequential Circuit Analysis}

Given a state machine has one input $x(t)$ and two-bit state $(Q_1(t),Q_0(t))$.
The machine is described by the following state equations.

\noindent
$Q_1(t+1)~=~ ~x (t) Q_0(t) + Q'_1(t),$

\noindent
$Q_0(t+1)~=~ Q_1(t) Q'_0 (t) + x'(t) Q'_1(t)$.

\noindent
Use two D flip-flops and a minimal sum-of-products network to
implement the machine.

\noindent
(i). Fill the state table of the system.

\begin{table}[!h]
    \centering
    \begin{tabular}{|c|c|c|c|c|c|c|c|}
        \hline
       $id$ & $Q_1(t)$ &  $ Q_0(t)$ & $x(t)$ & $Q_1(t+1)$ & $Q_0(t+1)$ & $D_1$ & $D_0$ \\ \hline
       0 & 0 & 0 & 0 &  & & &  \\ \hline
       1 & 0 & 0 & 1 &  & & &  \\ \hline
       2 & 0 & 1 & 0 &  & & &  \\ \hline
       3 & 0 & 1 & 1 &  & & &  \\ \hline
       4 & 1 & 0 & 0 &  & & &  \\ \hline
       5 & 1 & 0 & 1 &  & & &  \\ \hline
       6 & 1 & 1 & 0 &  & & &  \\ \hline
       7 & 1 & 1 & 1 &  & & &  \\ \hline
    \end{tabular}
\end{table}

\noindent
(ii). Describe the design using a logic diagram.
Show your derivation (K maps).

\end{document}