CSE 140 Syllabus

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Textbooks

Recommended Textbook :

• [Harris]: Digital Design and Computer Architecture by David Mooney Harris and Sarah L. Harris
• [Vahid]: Digital Design by Frank Vahid

Peer Instruction : Clickers

The course lectures will follow a Peer Instruction format, a teaching model which places stronger emphasis on classroom discussion and student interaction. As part of this, you will be assigned an iClicker, which you will need to register. You will be expected to have completed the assigned reading and ready to discuss with your classmates. The iClicker can be purchased at the UCSD book store.

Schedule

Date	Lecture	Topics	Note	Readings
Wed 01/07	1	Course Overview - The digital abstraction and basic logic gates [Slides]		[Harris] Chapter 1
Fri 01/09	2	Combinational Logic Specification and Realization: Truth tables, Boolean Algebra, Boolean Equations (sum of product) [Before Slides]		[Harris] Chapter 2, Section 2.1-2.4
Mon 01/12	3	Combinational Logic Specification and Simplification: POS and SOP canonical forms, Boolean Algebra Axioms - DeMorgan's, Consensus, Covering, reduction of boolean expressions using boolean algebra, bubble pushing [Before Slides]		[Harris] Chapter 2, Section 2.1-2.4
Wed 01/14	4	Combinational Circuits: Simplification using Boolean Algebra- Shannon Expansion, 2 variable K-maps [Before Slides]		[Harris] Chapter 2, Section 2.5, 2.7
Wed 01/14		HW 1 posted due 01/21
Fri 01/16		Quiz 1
Fri 01/16	5	Simplifying incompletely specified functions [Before Slides]		[Harris] Chapter 2, Section 2.7
Wed 01/21	6	Optimizing Combinational Circuits: Logic minimization with multivariable K-maps, essential and non-essential prime implicants [Before Slides]		[Harris] Chapter 2, Section 2.7
Wed 01/21		HW 2 posted, due 01/28
Fri 01/23	7	K-Maps with multiple solutions (essential and non-essential prime implicants and implicates) [Before Slides]
Mon 01/26	8	K-map to product of sum minimization K-Maps in higher dimensions [Before Slides]
Wed 01/28	9	Universal Gates [Before Slides]		[Harris] Chapter 2, Section 2.7
Wed 01/28		HW 3 posted due 02/11
Fri 01/30		Quiz 2
Fri 01/30	10	Sequential Network Components: Bistable memory elements, latches (SR) [Before Slides]		[Harris] Chapter 3, Section 3.1, 3.2
Mon 02/02	11	Sequential Network Components: Latches (SR,D), flip-flops (D) [Before Slides]		[Harris] Chapter 3, Section 3.1, 3.2
Wed 02/04	12	Sequential Network Components: flip-flops (D,JK,T) and Midterm Review [Before Slides]		[Harris] Chapter 3, Section 3.1, 3.2
Fri 02/06		Midterm 1
Mon 02/09	13	Sequential Network Specification: Finite State Machines [Before Slides]		[Harris] Chapter 3, Section 3.3, 3.4.1, 3.4.2
Wed 02/11	14	Sequential Network Implementation: Moore and Mealy Machines [Before Slides]		[Harris] Chapter 3, Section 3.4
Fri 02/13		Quiz 3
Fri 02/13	15	Sequential Network Implementation: Moore and Mealy Machines (contd.) [Before Slides]		[Harris] Chapter 3, Section 3.4
Sun 02/15		HW 4 posted due 02/25
Mon 02/16		Campus holiday
Wed 02/18	16	Sequential Network Specification: From circuit to FSM [Before Slides]		[Harris] Chapter 3, Section 3.4
Fri 02/20	17	Sequential Network Timing Analysis [Before Slides]		[Harris] Chapter 2 Section 2.8.2, other?
Mon 02/23		Quiz 4
Mon 02/23	18	Sequential Network Timing Analysis (contd.) [Before Slides]		[Harris] Chapter 2 Section 2.8.2, other?
Wed 02/25	19	Sequential Network Timing Analysis (contd.), Standard Modules (decoders) [Before Slides]		[Harris] Chapter 3, Section 3.5
Fri 02/27		Midterm 2
Sun 03/01		HW 5 posted due 03/08
Mon 03/02	21	RTL Design: High Level State Machines and Processor Design [Before Slides]		[Vahid] Chapter 5
Wed 03/04	22	RTL Design: From pseudocode to circuit [Before Slides] [Chapter 9 Lang]]		[Vahid] Chapter 5
Fri 03/06		Quiz 5
Fri 03/06	23	RTL Design: From pseudocode to circuit [Before Slides]		[Vahid] Chapter 5
Mon 03/09	24	RTL Design (contd) [Before Slides]
Wed 03/11	25	Final review 1(RTL Design, HLSMs and Timing)
Fri 03/13	26	Final review 2 (FSM Implementation)
03/14, 3pm - 6:00pm		Final Exam