Objective of this course is to introduce digital components & provide
hands-on experiences in building digital circuits using computer aided design
(CAD) software. Xilinx ISE 6.2i and Altera Quartus II.
Course Schedule:
Class:
W 5:00-6:20PM, Center 214
Final
Final
exam - 30% 7:00-8:20PM, Monday Dec. 5
Office Hours:
W
10:30-11:30AM (except 10/5), TH 9:30-10:30AM
TAs of CSE140L
Haikun Zhu
hazhu@cs
Rui
Shi rshi@cs
WebBoard for CSE140L
http://webboard.ucsd.edu
Lab Hours
Weekly Schedule
Extra Hours:
3:30p~7:00p, Tuesday, 10/25/05
3:30p~7:00p, Tuesday, 11/15/05
3:30p~7:00p, Tuesday, 11/22/05
3:30p~7:00p, Thursday, 12/01/05
NO lab hours on 11/11
Notices
There is NO
office hours on 10/05.
The name and email of students who are looking
for partner on CSE140L are listed on webboard. If you are looking for partner, please check it at
http://webboard.ucsd.edu -->
CSE 140L - Digital Systems Laboratory [FA
05] --> General Info -->
Students looking for lab partner
We will keep the list updated.
If you want to list your name there, please write email to us. And let us
know when you find partner.
The computers in B240/B250 only have Xilinx ISE 6.3i installed.
It is perfectly OK (actually it is expected) if you get different delay
numbers from 6.3i and 7.1i. You can use either version of the software, as
long as it's consistent. [10/13/05]
On some computers in B240/B250 the following two problems have been
reported:
--
"memory unreadable"
error messages during "implement
design" step.
--
unable to do ModelSim simulation due to lack of proper simulation libraries.
Currently we have no solution to these problems and ACS staff is working on
them. [10/13/05]
Sample & Solution for
final exam
Lab Notes:
Q & A for installation of Xilinx
ISE and ModelSim
Tutorial on how to build and simulate
a full adder in Xilinx
10/05 Lecture Slides
10/26 Lecture Slides
11/02 Lecture Slides
11/09 Lecture Slides
11/23 Lecture Slides
Tutorial
on how to design pattern recognizer in Xilinx
Labs
There
will be 4 labs (computer simulations & report write-up).
Work
in a group of two. One report per group.
Lab 1 ---
Combinational Circuit
Design: Ripple Adder, MUX and Comparator
Lab 1 Assignment (Updated on 10/13/05)
Due 10/26/05
Lab 1 FAQ
Lab 2 ---
The Specification and
Usage of Flip-Flops:
Shifter Register, Counters, Random Sequencer
Lab
2 Assignment (Updated on 10/31/05)
Due 11/16/05
Lab 3 ---
Finite State Machine:
Pattern Recognizer
Lab
3 Assignment (Updated on 11/19/05)
Due 11/23/05
Lab 3 FAQ
Lab 4 ---
Design of a mini load/store
computer system
Lab
4 Assignment (Updated on 11/29/05)
Due 12/02/05
Lab 4 Tutorial
Lab 4 FAQ