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Objective
In this lab, we will build a mini
load/store type computer system which consists of a program
counter, an ALU (Arithmetic Logic Unit), an
instruction decoder, three registers and a chunk of memory. We use buses and
various components from the Xilinx library to design the ALU, memory,
registers and program counter, and use VHDL code to design the
instruction decoder.
Note that in this lab, we use FPGA Family:
Spartan2, Device
Type: xc2s30-5tq144.
The Project
Design
a simple load/store type computer system that can perform addition, shift, comparison, and
masking. The system reads a 7-bit value
from the read-only memory (ROM) block (3-bit
instruction set & 4-bit data). The memory block should be able to
hold at least 16 instructions. There are three 4-bit registers R1, R2,
and R3. Registers R1 and R2 store the data. Register R3 presents the
result of the calculations. There are also a 1-bit flag for overflow
and another 1-bit flag for comparison. We list the specification
of the instructions:
|
Command
|
3-bit Inst.
|
4-bit Data
|
Description
|
|
1 Init
|
000
|
XXXX
|
Initialize all registers, ie R1=R2=R3=(0,0,0,0).
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2 Move1
|
001
|
aaaa
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Put aaaa value into register R1.
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3 Move2
|
010
|
bbbb
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Put bbbb value into register R2.
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|
4 Store
|
011
|
XXXX
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Take the previous result in R3 and store into register R1.
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5 Add
|
100
|
XXXX
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Add contents in R1 and R2. Present the result at R3 and output overflow flag.
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6 Comp |
101
|
XXXX
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Compare the contents of R1 and R2. The flag bit is false iff R2 > R1.
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7 Shift
|
110
|
aaXX
|
Left rotate
the content in R1 by aa bits,
then store the result in R3.
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8 Mask
|
111
|
XXXX
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Mask (AND-ing) R1 and R2. Present the result in R3.
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*For
4-bit data, X is Don't Care.
**Note that register R1 holds its
content except for instructions 1, 2 and 4; Register R2 holds except for
instructions 1 and 3; Register R3 holds except for instructions 1, 5, 7 and 8.
In addition, a program counter and an instruction
decoder are needed to make the whole system working.
Report
A. Title page:
- Names
of students and due date.
- Title
of the lab and objective.
-
A brief
description of each person's contribution.
Contents:
- Schematic diagrams of the top-level design, memory,
ALU (datapath), registers and program counter, must use
BUS. Also include the schematic diagrams of all
the basic function blocks (e.g. MUX) you create for your
design.
- VHDL code of
the instruction decoder.
- Layout of the
placed design (FPGA figure).
- Show your 16 instructions inside
ROM in a table including the index of instruction, the
command of instruction, the 3-bit instruction, the 4-bit
data and the expected content of all the registers (R1,
R2, R3, overflow, comparison).
Please follow the given command sequence, create data by
yourself and satisfy the requirements for each
operation.
|
No. |
Command
|
3-bit Inst.
|
4-bit Data
|
Requirement |
|
0 |
Init |
000
|
|
|
|
1 |
Move1 |
001
|
|
|
|
2 |
Move2 |
010
|
|
|
|
3 |
Add |
100 |
|
overflow = 0 |
|
4 |
Store |
011
|
|
content in R1 changed |
|
5 |
Move2 |
010 |
|
content in R2 changed |
|
6 |
Add |
100
|
|
overflow = 1 |
|
7 |
Move2 |
010 |
|
content
in R2 changed |
|
8 |
Comp |
101 |
|
R1 > R2 |
|
9 |
Move1 |
001 |
|
content
in R1 changed |
|
10 |
Comp |
101 |
|
R1 < R2 |
|
11 |
Move2 |
010 |
|
content
in R2 changed |
|
12 |
Comp |
101 |
|
R1 = R2 |
|
13 |
Mask |
111 |
|
content
in R3 changed |
|
14 |
Shift |
110 |
|
content
in R3 changed |
|
15 |
Init |
000 |
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- Functional simulation of
your 16 instructions. Behavior simulation waveforms to demonstrate the
value of program counter, instruction and all the
registers (R1, R2,R3, overflow, comparison) for every
instruction.
- Discussion of the verification.
- Timing
report.
- Illustrate
the worst delay from CLK to registers in post
place&route simulation waveforms.
Grading
90% will be based on the completeness and
correctness of the report.
10% will be based on the neatness, organization, and following instruction of
the report format.
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