Objective
Learn
how to design the pattern recognizer using finite state machine.
Learn
how to use the state diagram to specify the system as a finite state machine.
Learn
the VHDL implementation in Xilinx.
Learn
the difference between Mealy and Moore machines and compare their results
with different state assignments.
Note
that in the lab, we use Device Family: Spartan2, Device Type: xc2s30-5tq144.
Part
1. The Finite State Machine
Design the finite state machine
(Mealy Machine & Moore Machine) for a pattern recognizer, which
has a one-bit input, x, and a one-bit output, z. Whenever the input string x(t-5, t) matches the pattern "110010" or "110110", the
machine outputs a '1' . Otherwise, the output is '0'.
Overlaps of the patterns are allowed.
For this part, your
report should at least include:
-
A
summary for the design and implementation process with less than 80 words.
Part 2. Mealy Machine
-
Implement the pattern
recognizer as a Mealy machine in Xilinx. Try
three different coding for state assignments.
-
Verify the correctness of
the design. Given an input sequence
x="1110110010110010", display the simulation
waveforms.
-
Change the input sequence
to demonstrate the glitch of the Mealy machine.
For this part, your
report should at least include:
-
The
state diagram.
-
Three VHDL programs ( The
first VHDL codes should be complete. The other
two can only show the difference from the first one. )
- The
statistical information for state encoding and
device utilization from "Synthesis Report".
-
Post place&route
simulation waveforms
for that given input sequence.
-
Simulation waveforms with glitch and explain why
it happens or explain why there is no glitch.
Part 3. Moore Machine
-
Implement the pattern
recognizer as a Moore machine in Xilinx. Try
three different coding for state assignments.
-
Verify the correctness of
the design. Given an input sequence
x="1110110010110010", display the simulation
waveforms.
-
Demonstrate an input
sequence (if there is any) that causes a glitch in the
Moore machine.
For this part, your
report should at least include:
-
The
state diagram.
-
Three VHDL programs ( The
first VHDL codes should be complete. The other
two can only show the difference from the first one. )
- The
statistical information for state encoding and
device utilization from "Synthesis Report".
-
Post place&route
simulation waveforms for that given input
sequence.
-
Simulation waveforms with glitch or explain
why there is no glitch.
Part 4. Comparison
Compare the six different implementations
(three different state assignments for both Mealy and Moore machines) in
terms of the number of states, number of flip-flops, number of lines of the VHDL
code, and the number of CLBs (Combinational Logic Blocks). List your results
in a table format.
For this part, your
report should at least include:
- The comparison
table.
Additional
Instructions on the Report
Provide a title page
which includes:
Names,
PIDs
of the students and due date.
Title
of the lab.
A
brief description of each person's contribution.
Grading
90% will be
based on the completeness and correctness of the report.
10% will be based on the neatness, organization, and following instruction of
the report format.
