FAQ for CSE 140L Lab 3

Q1: The state machine wizard in StateCAD does not work on the lab machines.
        What should I do?

When you build the state diagram in StateCAD following the tutorial on lab machines, you may get a System Error: 'Unable to re-open file _import.dmo during import'.
If so, select File->Design Wizard and answer Yes for using current diagram. Then click Next to continue and follow the same process as in tutorial to create the template state diagram. Once you are in Optimization Wizard window, click Cancel to finish the Design Wizard process. You should have the template state diagram.
Or you can compose the state diagram manually. Look through the tool buttons located to the left of the design window. There are buttons for adding a state, a transition, and a reset. You can use the corresponding buttons to build the state diagram.

Q2: The VHDL code window does not show up when StateCAD generating VHDL
       codes for my state machines. What should I do?

On the lab machines, when generating VHDL codes from a state diagram, StateCAD can successfully compile your state diagram. But when it generates VHDL, it may complain at the last step and not show any VHDL codes. And you get a System Error: 'Unable to write profile when set_hdl_filename'. You can ignore this error and continue to next step by adding the VHDL source to the project.
Actually the VHDL codes should already be generated and stored to a file, in spite of the
error message. The VHDL code is named after the state diagram file with a different extension .vhd. (e.g., if the state diagram is named mealy.dia, the VHDL code filename will be mealy.vhd).

Q3: What's the purpose for manual state encodings?

The purpose is to show that different state encodings leads to different circuit implementation, and thus different hardware cost and performance of state machines. State encoding provides another dimension of optimizations. By default, the Xilinx synthesis tool uses one hot encodings for state machines to optimize speed.

There are many different methods of coding the states. And the codes are directly related to the Flip-Flops used in the design. For n bits codes, we will need n FFs because one FFs can output one bit signal. And the output signals from the FFs will form the codes and represent certain state. Following are several possible encoding methods (Prof. Cheng has taught them in class).
(1). Binary code
      Use binary numbers to encode the states.
      n bits binary code needs n FFs and can represent 2^n states.
(2). Gray code
      Adjacent Gray codes are different in only one bit.
      n bits Gray code needs n FFs and can represent 2^n states.
(3). Johnson code
      Use the output pattern of Johnson counter to encode the states.
      n bits Johnson code needs n FFs and can represent 2n states.
(4). One hot code
      Only one bit is '1' in the code for each state.
      n bits one hot code needs n FFs and can represent n states.

For example, encoding for 8 states:

	Binary Code (3bits)	Gray Code (3bits)	Johnson Code (4bits)	One Hot Code (8bits)
S0	000	000	0000	00000001
S1	001	001	0001	00000010
S2	010	011	0011	00000100
S3	011	010	0111	00001000
S4	100	110	1111	00010000
S5	101	111	1110	00100000
S6	110	101	1100	01000000
S7	111	100	1000	10000000

Q4: What's a glitch? How does it happen?

A glitch is an undesired output transition. It happens because of the transient output changes between multiple input transitions. For more details, please refer to the lecture notes.
Mealy machines is more likely to have glitches, because its output depends on the input, which may change at any time. Moore machines are less likely to generate glitches, since the output only depends on the flip-flop outputs, which may change at roughly the same time.

Q5: How to find the number of lines of VHDL codes?

Open the VHDL file in Xilinx, then right click in the file window and select Line Numbers option. The index of lines will be shown and you can get the total number of lines of the VHDL file.