CSE 140L Lab Two, Fall 2005, CK Cheng

The Specification and Usage of Flip-Flops:
Shifter Register, Counters, Random Sequencer

Due time: Right before class on 11/16/05

Objective

Learn the specification and usage of Flip-Flops.

Learn how to design the basic sequential components such as shifter registers, counters and random sequencers.

Note that in the lab, we use Device Family: Spartan2, Device Type: xc2s30-5tq144.

Part 1. Serial to Parallel Shifter Register

   Build a 4-bit serial to parallel shift register using four FDCEs.

1. Design and implement the circuit.
2. Verify the correctness of the design. Show exactly 10 clock cycles of behavior simulation result.
3. Demonstrate the critical path by timing simulation.

For this part, your report should at least include:
  - Schematic diagram of the 4-bit shift register;
  - Test Bench waveforms (in Xilinx) for behavior simulation;
  - Behavior simulation waveforms (in ModelSim);
  - Data Sheet Report in the Text-based Post-Place & Route Static Timing Report, 
     highlight the worst case delay;
  - Test Bench waveforms (in Xilinx) for post-place & route simulation; 
  - Post-place&Route simulation waveforms (in ModelSim) with the worst case delay marked.

Part 2. Asynchronous Counter

   Build a 4-bit asynchronous UP counter using four FTCEs and inverters.

1. Design and implement the circuit.
2. Verify the correctness of the design. Show exactly 16 clock cycles of behavior simulation result counting from 0 (0000) to 15 (1111).
3. Build a 8-bit asynchronous up counter using the 4-bit asynchronous up counter built in previous step. Create a test bench for post-place&route as follow:
       Clock High/Low Time: 6ns;
       Input Setup Time: 4ns;
       Output Valid Delay 1ns;
       CLR is valid until 110ns;
       Simulation End Time: 520ns.
   Simulate this test bench and mark the time point where the counter fails in simulation waveforms. Explain why it fails.

For this part, your report should at least include:
  - Schematic diagram of the 4-bit asynchronous up counter;
  - Test Bench waveforms (in Xilinx) for behavior simulation;
  - Behavior simulation waveforms (in ModelSim);
  - Data Sheet Report in the Text-based Post-Place & Route Static Timing Report,
     highlight the worst case delay;
  - Test Bench waveforms (in Xilinx) for post-place & route simulation; 
  - Post-place&Route simulation waveforms (in ModelSim) with the worst case delay marked.
  - Test Bench waveforms and post-place&route simulation waveforms for 8-bit asynchronous counter, explain when and why it fails.

Part 3. Synchronous Counter

   Build a 4-bit synchronous UP counter using four FDCEs and combinational gates.

1. Design and implement the circuit.
2. Verify the correctness of the design. Show exactly 18 clock cycles of behavior simulation result including counting from 0 (0000) to 15 (1111).
3. Demonstrate the critical path by timing simulation.

For this part, your report should at least include:
  - Schematic diagram of the 4-bit synchronous up counter;
  - Test Bench waveforms (in Xilinx) for behavior simulation;
  - Behavior simulation waveforms (in ModelSim);
  - Data Sheet Report in the Text-based Post-Place & Route Static Timing Report,
     highlight the worst case delay;
  - Test Bench waveforms (in Xilinx) for post-place & route simulation; 
  - Post-place&Route simulation waveforms (in ModelSim) with the worst case delay marked.

Part 4. Gray Counter

   Build a 4-bit up/down gray counter with using four FTCEs and combinational gates.
   There is an input control signal UD:
      When UD = 1, the counter counts the up sequence:
         0000, 0001, 0011, 0010, 0110, 0111, 0101,0100,
         1100, 1101, 1111, 1110, 1010, 1011, 1001,1000
      When UD = 0, the counter counts the down sequence:
         1000, 1001, 1011, 1010, 1110, 1111, 1101, 1100,
         0100, 0101, 0111, 0110, 0010, 0011, 0001, 0000

1. Design and implement the circuit.
2. Verify the correctness of the design. Show exactly 16 clock cycles of behavior simulation result for UP and DOWN respectively following the defined sequence.
3. Demonstrate the critical path by timing simulation.

For this part, your report should at least include:
  - Schematic diagram of the 4-bit gray counter;
  - Test Bench waveforms (in Xilinx) for behavior simulation;
  - Behavior simulation waveforms (in ModelSim);
  - Data Sheet Report in the Text-based Post-Place & Route Static Timing Report,
     highlight the worst case delay;
  - Test Bench waveforms (in Xilinx) for post-place & route simulation; 
  - Post-place&Route simulation waveforms (in ModelSim) with the worst case delay marked.

Part 5. Pseudo Random Sequencer

   Build a 4-bit Pseudo Random Sequencer using four FDPEs and a 2-input XOR gate. The initial value is "1111". Your design target is to maximize the period of the pseudo random sequence generated by the circuit.

1. Design and implement the circuit.
2. Verify the correctness of the design. Show exactly 16 clock cycles of behavior simulation result.
3. Demonstrate the critical path by timing simulation.

For this part, your report should at least include:
  - Schematic diagrams of the 4-bit Pseudo Random Sequencer;
  - Test Bench waveforms (in Xilinx) for behavior simulation;
  - Behavior simulation waveforms (in ModelSim), and list one complete period of the pseudo random numbers generated from the sequencer you built;
  - Data Sheet Report in the Text-based Post-Place & Route Static Timing Report,
     highlight the worst case delay;
  - Test Bench waveforms (in Xilinx) for post-place & route simulation; 
  - Post-place&Route simulation waveforms (in ModelSim) with the worst case delay marked.

Additional Instructions on the Report

   Provide a title page which includes:

Names, PIDs of the students and due date.

Title of the lab.

A brief description of each person's contribution.

Grading

   90% will be based on the completeness and correctness of the report.
   10% will be based on the neatness, organization, and following instruction of the report format.