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Objective
Learn
and get familiar with the Xilinx ISE FPGA design environment.
Learn
how to design the basic combinational digital components such as adders,
multiplexers and comparators.
Build
the concepts of function verification and timing analysis through out the
lab.
Note
that in the lab, we use Device Family: Spartan2, Device Type: xc2s30-5tq144.
Part 1.
Tutorial
Go through
the Xilinx
ISE 7 In-Depth Tutorial
(Chapter 3:
Schematic-Based Design, Chapter 4: Behavioral Simulation, Chapter 5: Design
Implementation, Chapter 6: Timing Simulation)
Write a summary commenting on the overall process of using Xilinx and
how to avoid possible mistakes in less than 60 words.
Part 2.
Adders
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I.
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In the
first step we will build&simulate a full adder using Xilinx program as
follows:
Schematic
entry of the adder;
Simulate
the behavior of the logic to verify the function;
Perform
the post-place&route simulation to demonstrate the worst delay of the
circuit. Mark the amount of the delay.
You can
follow the tutorial for this step.
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II.
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Using the
full adder built in I, build a 4-bit adder & simulate the 4-bit adder.
Verify the function and demonstrate the worst delay of the circuit.
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For this part, your report should at least include:
-
Schematic
diagrams of the 1-bit half adder, 1-bit full adder and the 4-bit adder;
- Test Bench waveforms (in Xilinx) of the 4-bit adder;
- Behavior simulation waveforms (in ModelSim) of the 4-bit adder;
- Data Sheet Report in the Text-based Post-Place & Route Static Timing
Report for the 4-bit adder, highlight the worst case delay;
- Test Bench waveforms (in Xilinx) for post-place & route 4-bit adder
verification;
- Post-place&Route simulation waveforms (in ModelSim) for the 4-bit adder
with the worst case delay marked. Explain when the worst case delay will
happen.
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Part 3.
Multiplexers
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A 2-to-1
multiplexer (MUX) selects one of the two input signals according to the control
signal:
Input: data signal A and B; control signal
ctrl.
Output: signal C;
Function: C=A if ctrl=0; C=B if ctrl=1.
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I.
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Build a
2-to-1 multiplexer using schematic entry in Xilinx.
Verify the function and demonstrate the worst delay of
the circuit.
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II.
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A 4-to-1
MUX selects one of the four input signals according to the control signal.
Define the specification for this 4-to-1 MUX, i.e., input, output &
their relationship.
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III.
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Build the
4-to-1 MUX using the 2-to-1 MUX built in I.
Verify the function and demonstrate the worst delay of
the circuit.
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For this part, your
report should at least include:
- Specification of the 4-to-1 MUX;
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Schematic
diagrams of the 2-to1 MUX and 4-to-1 MUX;
- Test Bench waveforms (in Xilinx) of the 2-to1 MUX and 4-to-1 MUX;
- Behavior simulation waveforms (in ModelSim) of the 2-to1 MUX and 4-to-1
MUX;
- Data Sheet Report in the Text-based Post-Place & Route Static Timing
Report for both the 2-to1 MUX and 4-to-1 MUX, highlight the worst case
delay;
- Test Bench waveforms (in Xilinx) for post-place & route 2-to1 MUX and
4-to-1 MUX verification;
- Post-place&Route simulation waveforms (in ModelSim) with the worst case
delay marked, for both the 2-to1 MUX and 4-to-1 MUX. Explain when the worst
case delay will happen.
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Part 4.
Comparator
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Build a
2-bit comparator defined as follows:
Input: 2-bit unsigned binary numbers
A[1:0], B[1:0]
Output: signal LE, EQ
Function: LE=1 iff A<B, LE=0 otherwise
EQ=1 iff A=B, EQ=0 otherwise
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I.
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Write out
the logic expressions for LE and EQ respectively with the goal to
minimize the number of terms.
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II.
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Build the
2-bit comparator in Xilinx. Verify the function and demonstrate the worst delay of
the circuit.
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III.
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Build
a 4-bit comparator using the 2-bit comparator.
Verify the
function and demonstrate the worst delay of the circuit.
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For this part, your
report should at least include:
-
Schematic
diagrams of the 2-bit and 4-bit comparators;
- Test Bench waveforms (in Xilinx) of the 2-bit and 4-bit comparators;
- Behavior simulation waveforms (in ModelSim) of the 2-bit and 4-bit
comparators;
- Data Sheet Report in the Text-based Post-Place & Route Static Timing
Report for both the 2-bit and 4-bit comparators, highlight the worst case
delays;
- Test Bench waveforms (in Xilinx) for post-place & route 2-bit and 4-bit
comparators;
- Post-place&Route simulation waveforms (in ModelSim) with the worst case
delay marked, for both the 2-bit and 4-bit comparators. Explain when the
worst case delay will happen.
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Additional
Instructions on the Report
Provide a title page
which includes:
Names,
PIDs
of the students and due date.
Title
of the lab.
A
brief description of each person's contribution.
Grading
90% will be
based on the completeness and correctness of the report.
10% will be based on the neatness, organization, and following instruction of
the report format.
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