Jingwei Lu's Homepage [Resume 1page, 2pages], [Google Scholar], [LinkedIn]

email: francesco DOT ljw AT gmail DOT com

Biography

Senior Software Engineer (L6) @ Amazon.com

Senior Principal Software Engineer (L7) @ Cadence Design Systems, Inc.

Ph.D. in Computer Science (Computer Engineering) @ University of California, San Diego

-- Advisor: Prof. Chung-Kuan Cheng
-- Thesis: Analytic VLSI Placement using Electrostatic Analogy

M.Phil in Computer Engineering @ The Hong Kong Polytechnic University

-- Advisor: Dr. Chiu-Wing Sham
-- Thesis: Fundamental Research on Electronic Design Automation in VLSI Design - Routability

B.S. in Information Engineering @ Zhejiang University

-- Advisor: Kuang Wang

Research

ePlace: Electrostatics based Placement

ePlace-MS: Electrostatics based Placement for Mixed-Size circuits

ePlace-3D: Electrostatics based Placement for 3D-ICs

Publications

Please be aware that all papers are copyrighted by the organization responsible for the corresponding conference or journal.

Conferences

J. Lu, H. Zhuang, I. Kang, P. Chen and C.-K. Cheng, "ePlace-3D: Electrostatics based Placement for 3D-ICs", ISPD 2016, pp. 11-18. (paper, slides).

X. Zhang, J. Lu, Y. Liu and C.-K. Cheng, "Worst-Case Noise Area Prediction of On-Chip Power Distribution Network", SLIP 2014, pp. 1-8. (paper, slides).

J. Lu, P. Chen, C.-C. Chang, L. Sha, D. J.-S. Huang, C.-C. Teng and C.-K. Cheng, "ePlace: Electrostatics Based Placement Using Nesterov's Method", DAC 2014, pp. 1-6. (nominated for best paper award, 12 out of 174 papers, 787 submissions) (paper, slides, poster).

J. Lu, P. Chen, C.-C. Chang, L. Sha, D. J.-S. Huang, C.-C. Teng and C.-K. Cheng, "FFTPL: An Analytic Placement Algorithm Using Fast Fourier Transform for Density Equalization", ASICON 2013, pp. 1-4. (paper, slides).

H. Zhuang, J. Lu, K. Samadi, Y. Du and C.-K. Cheng, "Performance-Driven Placement for Design of Rotation and Right Arithmetic Shifters in Monolithic 3D ICs", ICCCAS 2013, pp. 509-513. (paper, slides).

J. Lu and C.-W. Sham, "LMgr: A Low-Memory Global Router with Dynamic Topology Update and Bending-Aware Optimum Path Search", ISQED 2013, pp. 213-238 (best paper award, 3 out of 114 papers). (paper, slides).

S. K. Han, K. Jeong, A. B. Kahng and J. Lu, "Stability and Scalability in Global Routing", SLIP 2011, pp. 1-6. (paper, slides).

J. Lu, W.-K. Chow and C.-W. Sham, "Clock Network Synthesis with Concurrent Gate Insertion", PATMOS 2010, pp. 228-237. (paper, slides).

J. Lu, W.-K. Chow, C.-W. Sham and E. F. Y. Young, "A Dual-MST Approach for Clock Network Synthesis", ASPDAC 2010, pp. 467-473 (nominated for best paper award, 13 out of 115 papers, 340 submissions). (paper, slides).

Journals

J. Lu, H. Zhuang, P. Chen, H. Chang, C.-C. Chang, Y.-C. Wong, L. Sha, D. Huang, Y. Luo, C.-C. Teng and C.-K. Cheng, "ePlace-MS: Electrostatics based Placement for Mixed-Size Circuits", IEEE TCAD, 34(5) (2015), pp. 685-698. (paper).

J. Lu, P. Chen, C.-C. Chang, L. Sha, D. Huang, C.-C. Teng and C.-K. Cheng, "ePlace: Electrostatics based Placement using Fast Fourier Transform and Nesterov's Method", ACM TODAES, 20(2) (2015), article 17. (paper).

J. Lu, W.-K. Chow and C.-W. Sham, "Fast Power- and Slew-Aware Gated Clock Tree Synthesis", IEEE TVLSI, 20(11) (2012), pp. 2094-2103. (paper).

J. Lu, W.-K. Chow and C.-W. Sham, "A New Clock Network Synthesizer for Modern VLSI Designs", Integration, the VLSI Journal, 45(2) (2012), pp. 121-131 (Top 25 hotest ariticle in Integration, the VLSI journal of 2012). (paper).

C.-W. Sham, E. F. Y. Young and J. Lu, "Congestion Prediction in Early Stages of Physical Design", ACM TODAES, 14(1) (2009), (12:1-18). (paper).