Department of Computer Science and Engineering,
University of California, San Diego,
La Jolla, CA 92093-0404
Address for express mail:
9500 Gilman Dr., Building EBU3 Room 2130
CSE Dept., UC San Diego, La Jolla, CA 92093-0404
Email: ckcheng at ucsd dot edu,
Tel: (858) 534-6184,
Fax: (858) 534-7029
Google Scholar profile of C.K. Cheng
I am a Distinguished Professor at the Department of Computer Science and
Engineering and an Adjunct Professor at the Department of Electrical and
Computer Engineering, the University of California, San Diego. I have served
as a Senior Engineer, Principal Engineer, and Consultant at various System,
Design, and Electronic Desgin Automation Companies. I got my Ph.D. from
the Department of Electrical Engineering and Computer Science at the University
of California, Berkeley in 1984.
Star power, 2004
Annual event, 2005
Cruising in San Diego, 1/04/2007
IBM EIP Award at EPEP, 10/29/2007
CK Cheng, 1/05/2010
Thanksgiving luncheon, 11/22/2012
Start of MEG Project, 12/12/2013
UJIMA Award, 2/23/2013
Mentorship for 27 years, and keeps going, 8/30/2013
Prof. Graham's Birthday, Celebration Conference, 6/15-19/2015
Research group lunch meeting, 7/27/2016
Cadence Academic Collaboration Award, announced at ACM/IEEE DAC 2016, (photo taken 11/2/2016)
Thanksgiving luncheon, 12/3/2016
With the godfather of SPICE, Starting a new chapter of SPICE_Diego, 5/3/2017
Cadence Distinguished Lecture, 3/5/2018
Photo 2 ,
Commemoration for Prof. T.C. Hu, ACM ISPD 2018, 3/27/2018
Copper Harbor, and
Lake Superior ,
Michigan Technological University visit, 10/5/2018,
Pavilion of Harmony Chinese University of Hong Kong, Shatin visit, 12/13/2018,
Hosting Prof. Steve Kang, the coauthor of the fourth passive component,
Price Center, UC San Diego, 4/29/2019
Thanksgiving Dinner, 11/27/2019
List of Books for CK Group
Released Packages and Report
Ratio Cut Package, 1989-1995
RLC Reduction of Interconnect, 1999-2003
Floorplanning of Blocks, 1999-2001
Y Architecture, 2002-2003
FPGA Interconnect Architecture Package, 2006-2008
Eye Diagram Prediction Package, 2006-2008
Interconnect Architecture Topology Synthesis, 2006-2008
BSIM3 model to Matlab format, 2010-2013
Analytic Global Placement, 2019
ROAD Project: Routing Analysis, 2019.
RePlace, 2019, Github open source files:
Annimation of ePlace based clustering on Adapter2 case, 2/12/2020:
OpenRoad Project: Printed Circuit Board Layout Automation, 2019-
Incremental Detailed Routing Analysis and Optimization, 2019,
for the compressed tar file, ROAD_V1.0.tar.gz.
Top Level App:
Honors and Awards
NCR Best Teaching Award, School of Engineering, University of California,
San Diego, 1991.
IEEE Circuits and Systems Society, CAD Transactions Best Paper Awards, 1997, 2002.
IEEE Fellow, 2000.
IBM Faculty Awards, 2004, 2006, 2007.
Honorary Appointment as a Guest Professor of the Department of
Computer Science & Technology, Tsinghua University, 2002-2008.
Runner Up of Best Poster Award, Research Expo, School of Engineering, UCSD,
L. Zhang, High Performance Current-Mode Differential Logic,
out of 51 posters in Computer Science and Engineering Dept.,
Feb. 23, 2007.
Best Poster Award, Research Expo, School of Engineering, UCSD,
A. Shayan-Arani, X. Hu, Power Distribution Design for 3D Integration,
out of 60 posters in Computer Science and Engineering Dept, Feb. 19, 2009.
Distinguished Faculty Award, UJIMA Network, UC San Diego, 2013.
Distinguished Professor, UC San Diego, 2014.
Cadence Academic Collaboration Award, 2016.
ACM/IEEE ASPDAC Prolific Author Award, 2020.
Program Co-Chair, Int. Conf. on ASIC, ASICON, Oct. 2003.
Program Co-Chair, IEEE ASPDAC 2004.
Tutorial Co-Chair, IEEE ASPDAC 2005.
President 2003-2005, San Diego Chinese American Science and Engineering Association.
Tutorial Co-Chair, IEEE ASPDAC 2006.
One Day Tutorial Co-Organizer, ACM/IEEE DAC 2006.
Co-Chair, EDA Program, ICCCAS 2009.
General Chair, ACM/IEEE SLIP 2009.
UCSD Academic Senate Committee on Diversity and Equity (Member, Vice Chair, Chair, 2008-2011)
UCSD Academic Senate Committee on Faculty Welfare (Member, Chair, 2015-2018)
IEEE Transactions on Computer-Aided Design, Associate Editor, 2020-Present
ACM ISPD 2011 Talk in Commemoration of Ernest S. Kuh
Prof. Kuh and Us, ISPD 2011
Placement and Beyond in Honor of Ernest S. Kuh
VLSI CAD Symposium, Taiwan, 2015 Talk in Graduate Student Forum
The way to a successful career: graduate degree program
Cadence User Conference, Santa Clara, April 11, 2018
Physical layout for
3D IC placement and conditional routing rule management
CSE291: Interconnect and Packaging
CSE246: Computer Arithmetic Algorithms and Hardware Design Fall 2006
CSE291: Interconnection Networks Winter 2007
CSE242: Physical Layout Winter 2009
CSE20: Discrete Mathematics Winter 2010
ECE260B/CSE241A: Low Power VLSI Design Winter 2010
CSE140: Digital System Fall 2010
CSE140L: Digital System Labs Fall 2010
CSE249C: Mix Signal Verification Winter 2011
CSE20: Discret Mathematics Spring 2011
CSE291: Parallel Algorithms Spring 2011
CSE20: Discret Mathematics Spring 2012
CSE140: Digital Systems Fall 2012
CSE291: High Performance Interconnect Fall 2012
CSE245: Circuit Simulation and Verification Winter 2013
CSE140: Digital System Spring 2014
CSE291: Topics on Numeric Methods for Biosignal Processing Spring 2014
CSE140: Digital System Fall 2014
CSE245: Circuit Simulation Winter 2015
CSE291: Topics on Scientific Computation Fall 2015
CSE140: Digital System Winter 2016
CSE291: Convex Optimization Winter 2017
CSE140: Digital System Spring 2017
CSE291: Convex Optimization Fall 2017
CSE140: Digital System Spring 2018
CSE203B: Convex Optimization Winter 2019
CSE140: Digital System Spring 2019
CSE203B: Convex Optimization Winter 2020
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