| 1 |
1/6 |
Introduction |
slides notes |
| 2 |
1/8 |
Power; the memory hierarchy |
slides notes |
| 3 |
1/13 |
Vectorization and SIMD intsructions; |
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GPU Architecture |
slides notes |
| 4 |
1/15 |
CUDA Programming |
slides notes |
| 5 |
1/20 |
An improved matrix multiply; |
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Divergence |
slides notes |
| 6 |
1/22 |
Message passing; MPI |
slides notes |
| 7 |
1/27 |
Cannon’s algorithm; |
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Project presentations |
slides notes |
| 8 |
1/29 |
Communication Avoiding Algorithms |
slides notes |
| 9 |
2/3 |
MPI Implementation of Stencil Methods |
slides notes |
| 10 |
2/5 |
Multigrid; |
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GPU Implementation of stencil methods (I) |
slides notes |
| 11 |
2/10 |
GPU Implementation of stencil methods (II); |
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Automated translation |
slides notes |
| 12 |
2/12 |
Communication Overlap |
slides notes |
| 13 |
2/17 |
Heterogenous processing |
slides notes |
| 14 |
2/19 |
Stencil Optmization |
notes |
| 15 |
2/22 |
Stencil Optimization (II) |
notes |
| 16 |
2/24 |
Project Status Reports |
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| 17 |
3/3 |
Performance Tuning |
notes |
| 18 |
3/5 |
Architectural factors |
notes |
| 19-20 |
3/13 |
Final Project Presentations |
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