3 Today’s readings (Lecture 15, 2/24/2015)
A. Nguyen et al, 3.5-D Blocking Optimization for Stencil Computations on Modern CPUs and GPUs, SC 2010, pp. 1-13, Nov 2010. DOI: 10.1109/SC.2010.2
S. Kamil et al., An auto-tuning framework for parallel multicore stencil computations, 2010 IEEE Intl. Symp. Parallel & Distrib. Proc. (IPDPS 2010), pp. 1-12 (19-23 April 2010). DOI: 10.1109/IPDPS.2010.5470421
K. Datta et al., Stencil computation optimization and auto-tuning on state-of-the-art multicore architectures, Proc. 2008 ACM/IEEE Conf. on Supercomputing (SC08), Article No. 4 (2008).
C. Olschanowsky et al., A Study on Balancing Parallelism, Data Locality, and Recomputation in Existing PDE Solvers, Proc. SC14: Intl. Conf. for High Perf. Computing, Networking, Storage and Analysis, pp. 793-804 (16-21 Nov. 2014). DOI: 10.1109/SC.2014.70
Basu, Protonu, et al., Compiler generation and autotuning of communication-avoiding operators for geometric multigrid. 20th Intl Conf. High Performance Computing (HiPC), 2013.
D. Wonnacott, Using time skewing to eliminate idle time due to memory bandwidth and network limitations, Proc. 14th Intl Parallel and Distributed Proc. Symp. (IPDPS 2000), pp. 171-180, 2000. DOI: 10.1109/IPDPS.2000.845979. Time skewing is also known as tiling over time.
C. Ding and Y. He., A ghost cell expansion method for reducing communications in solving PDE problems,, Proc. 2001 ACM/IEEE Conf. Supercomputing (SC ’01)., DOI=10.1145/582034.582084. The original paper on using extra wide ghost regions, trading off message starts for redundant computation.
V. Bandishti, I. Pananilath and U. Bondhugula. Tiling stencil computations to maximize parallelism Proc. Intl. Conf. High Perf. Comput., Networking, Storage Anal. (SC ’12). Article 40 (11 pp.)
D. G. Wonnacott and M. M. Strout. On the scalability of loop tiling techniques, Proc 3rd Intl Workshop on Polyhedral Compilation Techniques (IMPACT), January 2013.