CSE 140L
Digital Systems Laboratory

WINTER 2006

10:00am – 11:20 pm Wednesday in HSS Room 1330

Instructor: Yun-Parn Thomas Lee (yunparn_lee@yahoo.com)

Office Hours: Appointment only

Prerequisites and Class Information for CSE 140L : Information regarding the structure and content of the course.

CSE 140 Homepage : Link to the theory course.

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Announcements:

• If you want to learn more information about RISC and MIPS systems, here are some references:
  RISC: Part-I, Part-II, Part-III
  MIPS: Schematics, Source code
  
  
• TA will post the Lab4 demonstration time table on the webboard. Each group should sign one
  10-minute slot, and everybody in the group should show up in the demonstration.
• If you have any question on lab2 grading, please come to TA’s office hour and ask regarding.
  
  
• TA office hours from 2/16 – 2/28:
  2/16 2:00pm – 3:30pm
  2/18 10:00am – 12:00pm
  2/28 10:00am – 12:00pm
• Correction: In Lab2 part5, it should be XNOR gate instead of XOR gate.
  
  
• Altera Quartus II tutorial for lab1 (lecture on 01/25/06).
• Quick references for Verilog and VHDL.
• Quartus II tutorials for Verilog and VHDL.
  
  
• CSE 140L course overview.
• If you have any problem with your webboard account or lab account in EBU3B-B270,
  please contact Academic Computing Services directly.
• The webboard is ready to use. There are two conferences: Lab Discussion and Lab Partner.
  If you are looking for lab partners or have questions want to discuss with your classmates,
  please post notes on the webboard.
• In this quarter, we use Altera Quartus II as the design tool for all labs. You can either
  use the software in EBU3B-B270, or download the software from Altera website and
  install on your own computer. Here’s the link:
  https://www.altera.com/support/software/download/altera_design/quartus_we/dnl-quartus_we.jsp
  You need to create an account to download and license the software.

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Projects:

Lab #	Lab Topic	Lab Due
1	Hierarchical Ripple Adder and MUX	02/01/06
2	The Specification and Usage of Flip-Flops	02/15/06
3	Finite State Machine	03/01/06
4	System Design using Datapath and Control Subsystems	03/15/06

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Lecture Notes:

Lecture #	Date	Day	Link
1	01/11	Wednesday	Lecture 1
2	01/18	Wednesday	Lecture 2
3	01/25	Wednesday	Lecture 3
4	02/01	Wednesday	Lecture 4
5	02/08	Wednesday	Lecture 5
6	02/15	Wednesday	Lecture 6
7	02/22	Wednesday	Lecture 7
8	03/01	Wednesday	Lecture 8
9	03/08	Wednesday	Lecture 9

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Grading:

• Projects: 70%
• Final exam: 30% (Tuesday, 3/21/2006, 9:00AM - 10:20AM @ HSS1330)

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TA Contact Information and Office Hours:

All office hours are held in EBU3B - B270.

	Monday	Tuesday	Wednesday	Thursday	Friday	Saturday
Jianhua Liu (j11liu@ucsd.edu)	3:00pm – 4:00pm		1:00pm –2:30pm	2:00pm – 3:00pm

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