CSE 141L Introduction to Computer Architecture Lab Summer 2009
Class Thu 6:00pm - 8:45pm, WLH 2005
Attention! No class on Tuesdays!

Change Log
  • Add several Verilog examples in "Xilinx and Verilog Resources". (8/13)
  • Slides for week 2, week 3 updated. (8/12)

    		•
    Textbook Recommended. Robert Reese & Mitchell Thornton, "Introduction to Logic Synthesis using Verilog HDL" Morgan & Claypool Publishers

    Instructor Isaac Chu, UCSD Visiting Faculty
    ichu@ece.ucsd.edu
    T.A. Labor Day's Holiday Special Office Hours
    Vasileios: Saturday 9/5 10am-2pm + 3-6pm
    Hung-wei: Sunday 9/6 1-6pm + 7-9pm
    Ankur: Monday (9/7) 1-5pm

    Hung-Wei Tseng
    h1tseng@cs.ucsd.edu
    Lab Office hours: Mon & Tue: 2-6pm
    2:30pm-6:00pm on 8/31
    1:00pm-5:30pm on 9/1

    Vasileios Kontorinis
    vkontori@cs.ucsd.edu
    Lab Office hours: Thu & Fri: 2-6pm

    Ankur Jain
    ajain@ucsd.edu
    Sat: 1-5pm
    Sun: 1-3pm
    Thu, Fri: 5-6pm


    Lab room : EBU3b Room B240
    Attention! If your group want to demo on Friday, please show up at 2pm to sign for a time slot! Any group cannot finish the demo before 6pm will be considered as late.
    Attention! Please include [CSE141L] before your e-mail topic!

    Course Plan Week 1 : Assignment #1, ISA & Assembler. Notes
    Attention! Assignment #1, Use this sequence: 1, 6, 31, 9, 3, 18, 17, 0, 1, 5 (10 numbers only, not 11).
    Week 2 : Assignment #2, Verilog HDL & Synthesis. Notes
    Week 3 : Assignment #3, More on Verilog HDL. Notes
    Please reference Chapter 4 of the textbook for your pipeline diagram.
    Week 4 : Assignment #4, Optimizing CPU. Notes
    Week 5 : Assignment #5, Finishing up your optimized CPU Notes
    No Final Exam

    Grading 20 % : Assignment 1
    Attention! Assignment #1, Use this sequence: 1, 6, 31, 9, 3, 18, 17, 0, 1, 5 (10 numbers only, not 11).
    20 % : Assignment 2
    20 % : Assignment 3
    20 % : Assignment 4
    20 % : Assignment 5
    Please attend the lab lectures to obtain detail info about each assignment.

    Xilinx and Verilog Resources
  • Verilog Examples:
  • Download Xilinx Tools
    1. Go to the Xilinx download web page
    2. Select "Login to start downloading"
    3. Register or Sign in
    4. In quick links, select "Register and download 10.1 and earlier software"
  • http://www.cse.ucsd.edu/classes/su08/cse140L/140L_tutorial_1_-_summer_2008.pdf
    Xilinx Schematics tutorial from cse140L Summer 2008
  • http://www.cse.ucsd.edu/classes/su08/cse140L/140L_tutorial_1_-_summer_2008.pdf
    Xilinx Schematics tutorial from cse140L Summer 2007
  • http://www.cse.ucsd.edu/classes/su07/cse140L/140L_tutorial_1_-_summer_2007.pdf
  • http://www.cse.ucsd.edu/classes/su07/cse140L/140L_tutorial_2_-_summer_2007.pdf

    Xilinx Verliog/VHDL tutorial from cse140L Summer 2007
  • http://www.cse.ucsd.edu/classes/su07/cse140L/140L_tutorial_3_-_summer_2007.pdf

    Verilog Overview/tutorial by Sat Garcia
  • http://www.cse.ucsd.edu/classes/sp07/cse141/slides/vlog-tutorial.pdf
  • http://csg.csail.mit.edu/6.375/handouts/lectures/L03-Verilog-Design-Examples-1.pdf

    At some point, we will attempt to synthesize our circuits (e.g., to extract timing). These resources were selected because they should all be synthesis friendly. Many tutorials and verilog code available on the internet are not.