`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    20:10:19 06/19/2009 
// Design Name: 
// Module Name:    SingleCycle 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module SingleCycle(clk, out);
	input clk;
	output out;

	reg [31:0] pc;						// program counter
	reg [31:0] Registers [0:31];	// 32 32-bit registers
	reg [31:0] RAM[0:31];			// 32 32-bit data RAM
	reg [31:0] ROM [0:127]; 		// 128 32-bit instruction memory

	reg [31:0] instruction;			// instruction
	integer i;

	assign out = pc;
	
	initial // execute once only
	begin
		pc = 0;

		for (i = 0; i < 32; i = i + 1)
		begin
			Registers[i] <= 32'b00000000000000000000000000000000;
		end
		for (i = 0; i < 32; i = i + 1)
		begin
			RAM[i] <= 32'b00000000000000000000000000000000;
		end
 
		ROM[0] <= 32'b00000000000000000000000000000000;
		ROM[1] <= 32'b00000000000000000000000000000000;
		ROM[2] <= 32'b00000000000000000000000000000000;
		ROM[3] <= 32'b00000000000000000000000000000000;
		ROM[4] <= 32'b00000000000000000000000000000000;
		ROM[5] <= 32'b00000000000000000000000000000000;
		ROM[6] <= 32'b00000000000000000000000000000000;
		ROM[7] <= 32'b00000000000000000000000000000000;
		ROM[8] <= 32'b00000000000000000000000000000000;
		ROM[9] <= 32'b00000000000000000000000000000000;
		ROM[10] <= 32'b00110000000010000000000000000101;
		ROM[11] <= 32'b10101100010010000000000000000000;
		ROM[12] <= 32'b00000000000000000000000000000000;
		ROM[13] <= 32'b00110000000010000000000000000010;
		ROM[14] <= 32'b10101100010010000000000000000100;
		ROM[15] <= 32'b00000000000000000000000000000000;
		ROM[16] <= 32'b00110000000010000000000000001001;
		ROM[17] <= 32'b10101100010010000000000000001000;
		ROM[18] <= 32'b00000000000000000000000000000000;
		ROM[19] <= 32'b00110000000010000000000000000001;
		ROM[20] <= 32'b10101100010010000000000000001100;
		ROM[21] <= 32'b00000000000000000000000000000000;
		ROM[22] <= 32'b00110000000010000000000000000100;
		ROM[23] <= 32'b10101100010010000000000000010000;
		ROM[24] <= 32'b00000000000000000000000000000000;
		ROM[25] <= 32'b00100000000010000000000000000000;
		ROM[26] <= 32'b00100000010010010000000000010100;
		ROM[27] <= 32'b00000000000000000000000000000000;
		ROM[28] <= 32'b00000000000000000000000000000000;
		ROM[29] <= 32'b00000000000000100100000000100101;
		ROM[30] <= 32'b00100001000010001111111111111100;
		ROM[31] <= 32'b00100000010010110000000000010000;
		ROM[32] <= 32'b00100001000010101111111111111100;
		ROM[33] <= 32'b00000000000000000000000000000000;
		ROM[34] <= 32'b00000000000000000000000000000000;
		ROM[35] <= 32'b00000000000000000000000000000000;
		ROM[36] <= 32'b00100001000010000000000000000100;
		ROM[37] <= 32'b00010001010010000000000000111011;
		ROM[38] <= 32'b00000000000010000101000000100101;
		ROM[39] <= 32'b00000000000000000000000000000000;
		ROM[40] <= 32'b00000000000000000000000000000000;
		ROM[41] <= 32'b00100001010010100000000000000100;
		ROM[42] <= 32'b00000000000000000000000000000000;
		ROM[43] <= 32'b10001101000001000000000000000000;
		ROM[44] <= 32'b10001101010001010000000000000000;
		ROM[45] <= 32'b00000000000000000000000000000000;
		ROM[46] <= 32'b00000000100001011100000000101010;
		ROM[47] <= 32'b00010000000110000000000000110010;
		ROM[48] <= 32'b00000000000000000000000000000000;
		ROM[49] <= 32'b00001000000000000000000000110110;
		ROM[50] <= 32'b00000000000000000000000000000000;
		ROM[51] <= 32'b10101101010001000000000000000000;
		ROM[52] <= 32'b10101101000001010000000000000000;
		ROM[53] <= 32'b00000000000000000000000000000000;
		ROM[54] <= 32'b00000000000000000000000000000000;
		ROM[55] <= 32'b00010001011010100000000000100011;
		ROM[56] <= 32'b00001000000000000000000000101000;
		ROM[57] <= 32'b00000000000000000000000000000000;
		ROM[58] <= 32'b00000000000000000000000000000000;
		ROM[59] <= 32'b00000000000000000000000000000000;
		ROM[60] <= 32'b00000000000000000000000000000000;
		ROM[61] <= 32'b00100000010010010000000000010100;
		ROM[62] <= 32'b00000000000000100100000000100101;
		ROM[63] <= 32'b00000000000000000000000000000000;
		ROM[64] <= 32'b00000000000000000000000000000000;
		ROM[65] <= 32'b00000000000000000000000000000000;
		ROM[66] <= 32'b00010001000010010000000001001011;
		ROM[67] <= 32'b00000000000000000000000000000000;
		ROM[68] <= 32'b10001101000001000000000000000000;
		ROM[69] <= 32'b00110000000000100000000000000001;
		ROM[70] <= 32'b00000000000000000000000000000000;
		ROM[71] <= 32'b00000000000000000000000000000000;
		ROM[72] <= 32'b00100001000010000000000000000100;
		ROM[73] <= 32'b00001000000000000000000001000001;
		ROM[74] <= 32'b00000000000000000000000000000000;
		ROM[75] <= 32'b00000000000000000000000000000000;
		ROM[76] <= 32'b00000000000000000000000000000000;
		ROM[77] <= 32'b00000000000000000000000000000000;
		ROM[78] <= 32'b00000000000000000000000000000000;


		for (i = 79; i < 128; i = i + 1)
		begin
			ROM[i] <= 32'b00000000000000000000000000000000;
		end
		
	end
	
	always @(posedge clk) // execute each time clk changes from 0 to 1
	begin
		pc = pc + 1;
		instruction = ROM[pc];
		if (instruction[31:26] == 6'b000000) // R-type
		begin
			if (instruction[5:0] == 6'b100000)	// add
            Registers[instruction[15:11]] = Registers[instruction[25:21]] + Registers[instruction[20:16]];
         else if (instruction[5:0] == 6'b100010) // sub
            Registers[instruction[15:11]] = Registers[instruction[25:21]] - Registers[instruction[20:16]];
         else if (instruction[5:0] == 6'b100100) // and
            Registers[instruction[15:11]] = Registers[instruction[25:21]] & Registers[instruction[20:16]];
         else if (instruction[5:0] == 6'b100101) // or
            Registers[instruction[15:11]] = Registers[instruction[25:21]] | Registers[instruction[20:16]];
         else if (instruction[5:0] == 6'b101010) // slt
			begin
            if (Registers[instruction[25:21]] < Registers[instruction[20:16]])
              	Registers[instruction[15:11]] = 32'b00000000000000000000000000000001;
				else	
              	Registers[instruction[15:11]] = 32'b00000000000000000000000000000000;
			end
		end
		else if (instruction[31:26] == 6'b001100) // ori
		begin
         Registers[instruction[20:16]] = Registers[instruction[25:21]] | {16'b0000000000000000, instruction[15:0]};
		end
		else if (instruction[31:26] == 6'b001000) // addi
		begin
			if (instruction[15] == 1'b1)
				Registers[instruction[20:16]] = Registers[instruction[25:21]] + {16'b1111111111111111, instruction[15:0]};
			else
				Registers[instruction[20:16]] = Registers[instruction[25:21]] + {16'b0000000000000000, instruction[15:0]};
		end
		else if (instruction[31:26] == 6'b100011) // lw
		begin
         Registers[instruction[20:16]] = RAM[({16'b0000000000000000, instruction[15:0]} + Registers[instruction[25:21]]) >> 2];
		end
		else if (instruction[31:26] == 6'b101011) // sw
		begin
			RAM[({16'b0000000000000000, instruction[15:0]} + Registers[instruction[25:21]]) >> 2] = Registers[instruction[20:16]];
		end
		else if (instruction[31:26] == 6'b000100) // beq
		begin
			if (Registers[instruction[25:21]] == Registers[instruction[20:16]])
			begin
				pc = {16'b0000000000000000, instruction[15:0]};
			end
		end
		else if (instruction[31:26] == 6'b000010) // j
		begin
			pc = {16'b0000000000000000, instruction[15:0]};
		end
	end

endmodule