`timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Company: // Engineer: // // Create Date: 20:10:19 06/19/2009 // Design Name: // Module Name: SingleCycle // Project Name: // Target Devices: // Tool versions: // Description: // // Dependencies: // // Revision: // Revision 0.01 - File Created // Additional Comments: // ////////////////////////////////////////////////////////////////////////////////// module SingleCycle(clk, out, resetn); input clk; input resetn; output [31:0] out; reg [31:0] pc; // program counter reg [31:0] Registers [0:31]; // 32 32-bit registers reg [31:0] RAM[0:31]; // 32 32-bit data RAM reg [31:0] ROM [0:78]; // 78 32-bit instruction memory reg [31:0] instruction; // instruction integer i; reg [31:0] hold; reg [31:0] pointer; // Opcode parameter alu_operation = 6'b000000; parameter ori = 6'b001100; parameter addi = 6'b001000; parameter lw = 6'b100011; parameter sw = 6'b101011; parameter beq = 6'b000100; parameter jump = 6'b000010; // Alu operations parameter alu_add = 6'b100000; parameter alu_sub = 6'b100010; parameter alu_and = 6'b100100; parameter alu_or = 6'b100101; parameter alu_slt = 6'b101010; wire[5:0] op_code = instruction[31:26]; wire[5:0] operand1 = instruction[25:21]; wire[5:0] operand2 = instruction[20:16]; wire[5:0] operand3 = instruction[15:11]; wire[5:0] operand4 = instruction[10:6]; wire[5:0] alu_op = instruction[5:0]; assign out = instruction; always @(posedge clk or negedge resetn) begin if (!resetn) begin Registers[0] <= 32'h00000000; Registers[1] <= 32'h00000000; Registers[2] <= 32'h00000000; Registers[3] <= 32'h00000000; Registers[4] <= 32'h00000000; Registers[5] <= 32'h00000000; Registers[6] <= 32'h00000000; Registers[7] <= 32'h00000000; Registers[8] <= 32'h00000000; Registers[9] <= 32'h00000000; Registers[10] <= 32'h00000000; Registers[11] <= 32'h00000000; Registers[12] <= 32'h00000000; Registers[13] <= 32'h00000000; Registers[14] <= 32'h00000000; Registers[15] <= 32'h00000000; Registers[16] <= 32'h00000000; Registers[17] <= 32'h00000000; Registers[18] <= 32'h00000000; Registers[19] <= 32'h00000000; Registers[20] <= 32'h00000000; Registers[21] <= 32'h00000000; Registers[22] <= 32'h00000000; Registers[23] <= 32'h00000000; Registers[24] <= 32'h00000000; Registers[25] <= 32'h00000000; Registers[26] <= 32'h00000000; Registers[27] <= 32'h00000000; Registers[28] <= 32'h00000000; Registers[29] <= 32'h00000000; Registers[30] <= 32'h00000000; Registers[31] <= 32'h00000000; end else begin case (op_code) // R-type alu_operation : case (alu_op) alu_add : Registers[operand3] <= Registers[operand1] + Registers[operand2]; alu_sub : Registers[operand3] <= Registers[operand1] - Registers[operand2]; alu_and : Registers[operand3] <= Registers[operand1] & Registers[operand2]; alu_or : Registers[operand3] <= Registers[operand1] | Registers[operand2]; alu_slt : begin if (Registers[operand1] < Registers[operand2]) Registers[operand3] <= 32'h00000001; else Registers[operand3] <= 32'h00000000; end endcase ori : Registers[operand2] <= Registers[operand1] | {16'b0000000000000000, instruction[15:0]}; addi : if (instruction[15] == 1'b1) Registers[operand2] <= Registers[operand1] + {16'b1111111111111111, instruction[15:0]}; else Registers[operand2] <= Registers[operand1] + {16'b0000000000000000, instruction[15:0]}; lw : Registers[operand2] <= RAM[pointer]; endcase end end always @(posedge clk or negedge resetn) begin if (!resetn) instruction <= 32'h00000000; else instruction <= ROM[pc]; end // always @(instruction or Registers or operand1) always @(instruction or Registers or operand1) begin pointer = ({16'h0000,instruction[15:0]} + Registers[operand1]) >> 2; end always @(posedge clk or negedge resetn) begin if (!resetn) begin RAM[0] <= 32'h00000000; RAM[1] <= 32'h00000000; RAM[2] <= 32'h00000000; RAM[3] <= 32'h00000000; RAM[4] <= 32'h00000000; RAM[5] <= 32'h00000000; RAM[6] <= 32'h00000000; RAM[7] <= 32'h00000000; RAM[8] <= 32'h00000000; RAM[9] <= 32'h00000000; RAM[10] <= 32'h00000000; RAM[11] <= 32'h00000000; RAM[12] <= 32'h00000000; RAM[13] <= 32'h00000000; RAM[14] <= 32'h00000000; RAM[15] <= 32'h00000000; RAM[16] <= 32'h00000000; RAM[17] <= 32'h00000000; RAM[18] <= 32'h00000000; RAM[19] <= 32'h00000000; RAM[20] <= 32'h00000000; RAM[21] <= 32'h00000000; RAM[22] <= 32'h00000000; RAM[23] <= 32'h00000000; RAM[24] <= 32'h00000000; RAM[25] <= 32'h00000000; RAM[26] <= 32'h00000000; RAM[27] <= 32'h00000000; RAM[28] <= 32'h00000000; RAM[29] <= 32'h00000000; RAM[30] <= 32'h00000000; RAM[31] <= 32'h00000000; end else begin case (op_code) sw : RAM[pointer] <= Registers[operand2]; endcase end end always @(posedge clk or negedge resetn) begin if (!resetn) pc <= 32'h00000000; else begin pc <= pc + 32'h00000001; case (op_code) beq : if (Registers[operand1] == Registers[operand2]) pc <= {16'h0000, instruction[15:0]}; jump : pc <= {16'h0000, instruction[15:0]}; endcase end end always @(posedge clk or negedge resetn) begin if (!resetn) hold <= 32'h00000000; else hold <= 32'h00000000; end always @(posedge clk or negedge resetn) begin if (!resetn) begin ROM[0] <= 32'b00000000000000000000000000000000; ROM[1] <= 32'b00000000000000000000000000000000; ROM[2] <= 32'b00000000000000000000000000000000; ROM[3] <= 32'b00000000000000000000000000000000; ROM[4] <= 32'b00000000000000000000000000000000; ROM[5] <= 32'b00000000000000000000000000000000; ROM[6] <= 32'b00000000000000000000000000000000; ROM[7] <= 32'b00000000000000000000000000000000; ROM[8] <= 32'b00000000000000000000000000000000; ROM[9] <= 32'b00000000000000000000000000000000; ROM[10] <= 32'b00110000000010000000000000000101; ROM[11] <= 32'b10101100010010000000000000000000; ROM[12] <= 32'b00000000000000000000000000000000; ROM[13] <= 32'b00110000000010000000000000000010; ROM[14] <= 32'b10101100010010000000000000000100; ROM[15] <= 32'b00000000000000000000000000000000; ROM[16] <= 32'b00110000000010000000000000001001; ROM[17] <= 32'b10101100010010000000000000001000; ROM[18] <= 32'b00000000000000000000000000000000; ROM[19] <= 32'b00110000000010000000000000000001; ROM[20] <= 32'b10101100010010000000000000001100; ROM[21] <= 32'b00000000000000000000000000000000; ROM[22] <= 32'b00110000000010000000000000000100; ROM[23] <= 32'b10101100010010000000000000010000; ROM[24] <= 32'b00000000000000000000000000000000; ROM[25] <= 32'b00100000000010000000000000000000; ROM[26] <= 32'b00100000010010010000000000010100; ROM[27] <= 32'b00000000000000000000000000000000; ROM[28] <= 32'b00000000000000000000000000000000; ROM[29] <= 32'b00000000000000100100000000100101; ROM[30] <= 32'b00100001000010001111111111111100; ROM[31] <= 32'b00100000010010110000000000010000; ROM[32] <= 32'b00100001000010101111111111111100; ROM[33] <= 32'b00000000000000000000000000000000; ROM[34] <= 32'b00000000000000000000000000000000; ROM[35] <= 32'b00000000000000000000000000000000; ROM[36] <= 32'b00100001000010000000000000000100; ROM[37] <= 32'b00010001010010000000000000111011; ROM[38] <= 32'b00000000000010000101000000100101; ROM[39] <= 32'b00000000000000000000000000000000; ROM[40] <= 32'b00000000000000000000000000000000; ROM[41] <= 32'b00100001010010100000000000000100; ROM[42] <= 32'b00000000000000000000000000000000; ROM[43] <= 32'b10001101000001000000000000000000; ROM[44] <= 32'b10001101010001010000000000000000; ROM[45] <= 32'b00000000000000000000000000000000; ROM[46] <= 32'b00000000100001011100000000101010; ROM[47] <= 32'b00010000000110000000000000110010; ROM[48] <= 32'b00000000000000000000000000000000; ROM[49] <= 32'b00001000000000000000000000110110; ROM[50] <= 32'b00000000000000000000000000000000; ROM[51] <= 32'b10101101010001000000000000000000; ROM[52] <= 32'b10101101000001010000000000000000; ROM[53] <= 32'b00000000000000000000000000000000; ROM[54] <= 32'b00000000000000000000000000000000; ROM[55] <= 32'b00010001011010100000000000100011; ROM[56] <= 32'b00001000000000000000000000101000; ROM[57] <= 32'b00000000000000000000000000000000; ROM[58] <= 32'b00000000000000000000000000000000; ROM[59] <= 32'b00000000000000000000000000000000; ROM[60] <= 32'b00000000000000000000000000000000; ROM[61] <= 32'b00100000010010010000000000010100; ROM[62] <= 32'b00000000000000100100000000100101; ROM[63] <= 32'b00000000000000000000000000000000; ROM[64] <= 32'b00000000000000000000000000000000; ROM[65] <= 32'b00000000000000000000000000000000; ROM[66] <= 32'b00010001000010010000000001001011; ROM[67] <= 32'b00000000000000000000000000000000; ROM[68] <= 32'b10001101000001000000000000000000; ROM[69] <= 32'b00110000000000100000000000000001; ROM[70] <= 32'b00000000000000000000000000000000; ROM[71] <= 32'b00000000000000000000000000000000; ROM[72] <= 32'b00100001000010000000000000000100; ROM[73] <= 32'b00001000000000000000000001000001; ROM[74] <= 32'b00000000000000000000000000000000; ROM[75] <= 32'b00000000000000000000000000000000; ROM[76] <= 32'b00000000000000000000000000000000; ROM[77] <= 32'b00000000000000000000000000000000; ROM[78] <= 32'b00000000000000000000000000000000; end else begin // you can use hex or octal to reduce bits and improve readability ROM[0] <= 32'h00000000; ROM[1] <= 32'h00000000; ROM[2] <= 32'h00000000; ROM[3] <= 32'h00000000; ROM[4] <= 32'h00000000; ROM[5] <= 32'h00000000; ROM[6] <= 32'h00000000; ROM[7] <= 32'h00000000; ROM[8] <= 32'h00000000; ROM[9] <= 32'h00000000; ROM[10] <= 32'h30080005; ROM[11] <= 32'b10101100010010000000000000000000; ROM[12] <= 32'b00000000000000000000000000000000; ROM[13] <= 32'b00110000000010000000000000000010; ROM[14] <= 32'b10101100010010000000000000000100; ROM[15] <= 32'b00000000000000000000000000000000; ROM[16] <= 32'b00110000000010000000000000001001; ROM[17] <= 32'b10101100010010000000000000001000; ROM[18] <= 32'b00000000000000000000000000000000; ROM[19] <= 32'b00110000000010000000000000000001; ROM[20] <= 32'b10101100010010000000000000001100; ROM[21] <= 32'b00000000000000000000000000000000; ROM[22] <= 32'b00110000000010000000000000000100; ROM[23] <= 32'b10101100010010000000000000010000; ROM[24] <= 32'b00000000000000000000000000000000; ROM[25] <= 32'b00100000000010000000000000000000; ROM[26] <= 32'b00100000010010010000000000010100; ROM[27] <= 32'b00000000000000000000000000000000; ROM[28] <= 32'b00000000000000000000000000000000; ROM[29] <= 32'b00000000000000100100000000100101; ROM[30] <= 32'b00100001000010001111111111111100; ROM[31] <= 32'b00100000010010110000000000010000; ROM[32] <= 32'b00100001000010101111111111111100; ROM[33] <= 32'b00000000000000000000000000000000; ROM[34] <= 32'b00000000000000000000000000000000; ROM[35] <= 32'b00000000000000000000000000000000; ROM[36] <= 32'b00100001000010000000000000000100; ROM[37] <= 32'b00010001010010000000000000111011; ROM[38] <= 32'b00000000000010000101000000100101; ROM[39] <= 32'b00000000000000000000000000000000; ROM[40] <= 32'b00000000000000000000000000000000; ROM[41] <= 32'b00100001010010100000000000000100; ROM[42] <= 32'b00000000000000000000000000000000; ROM[43] <= 32'b10001101000001000000000000000000; ROM[44] <= 32'b10001101010001010000000000000000; ROM[45] <= 32'b00000000000000000000000000000000; ROM[46] <= 32'b00000000100001011100000000101010; ROM[47] <= 32'b00010000000110000000000000110010; ROM[48] <= 32'b00000000000000000000000000000000; ROM[49] <= 32'b00001000000000000000000000110110; ROM[50] <= 32'b00000000000000000000000000000000; ROM[51] <= 32'b10101101010001000000000000000000; ROM[52] <= 32'b10101101000001010000000000000000; ROM[53] <= 32'b00000000000000000000000000000000; ROM[54] <= 32'b00000000000000000000000000000000; ROM[55] <= 32'b00010001011010100000000000100011; ROM[56] <= 32'b00001000000000000000000000101000; ROM[57] <= 32'b00000000000000000000000000000000; ROM[58] <= 32'b00000000000000000000000000000000; ROM[59] <= 32'b00000000000000000000000000000000; ROM[60] <= 32'b00000000000000000000000000000000; ROM[61] <= 32'b00100000010010010000000000010100; ROM[62] <= 32'b00000000000000100100000000100101; ROM[63] <= 32'b00000000000000000000000000000000; ROM[64] <= 32'b00000000000000000000000000000000; ROM[65] <= 32'b00000000000000000000000000000000; ROM[66] <= 32'b00010001000010010000000001001011; ROM[67] <= 32'b00000000000000000000000000000000; ROM[68] <= 32'b10001101000001000000000000000000; ROM[69] <= 32'b00110000000000100000000000000001; ROM[70] <= 32'b00000000000000000000000000000000; ROM[71] <= 32'b00000000000000000000000000000000; ROM[72] <= 32'b00100001000010000000000000000100; ROM[73] <= 32'b00001000000000000000000001000001; ROM[74] <= 32'b00000000000000000000000000000000; ROM[75] <= 32'b00000000000000000000000000000000; ROM[76] <= 32'b00000000000000000000000000000000; ROM[77] <= 32'b00000000000000000000000000000000; ROM[78] <= 32'b00000000000000000000000000000000; end end endmodule