`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   21:05:27 06/22/2009
// Design Name:   SingleCycle
// Module Name:   C:/Xilinx/CPU1/SingleCycleTest.v
// Project Name:  CPU1
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: SingleCycle
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module SingleCycleTest_v;

	// Inputs
	reg clk;
	// wire[31:0] out;
	
	// Instantiate the Unit Under Test (UUT)
	SingleCycle uut (
		.clk(clk),
		.out(out)
	);

	initial begin
		// Initialize Inputs
		clk = 0;

		// Wait 100 ns for global reset to finish
		#10;
	end
      
	always begin
		#10
		clk = !clk;
	end
	
endmodule