Lab Overview:

Lab Deliverables:

In order to make the work more manageable, there will be two due dates for this part of the lab. A preliminary progress report with the work from steps 1-3 will be due on Friday, Nov. 21. A full progress report, including all of the steps will be due on Monday, Dec. 1.

• Demonstration: None
• Progress Report: Once again, there are questions scattered throughout this lab that you should answer for your progress report. For questions that required a screen capture, make sure you fully describe the screenshot. You will also need to include all of the Verilog files from your project (*.v, *.tbw, *.ngc, *.mif, *.coe, etc.). Make sure your code is written in a clear and consistant style with liberal use of comments.

You will need to e-mail your ZIP file to Sat with the following naming convention for the subject: [CSE141L] Lab 3, Part B Preliminary Submission - Last Name 1, First Name 1 & Last Name 2, First Name 2. Again, for the final version, leave out "Preliminary" from the subject line.

Lab Description:

Step 1: Control Logic

Complete your execution unit by implementing its control logic. Include the source files in an appendix at the end of your progress report.

Step 2: Finalize Fetch Unit

Step 3: Instruction Set Test

Important Note:

Step 4: IO Test

Step 5: Write a Simple Loader

To run a SuperGarbage program using your VM, your processor first needs to properly load the application into the data memory. The following figure shows the format of the SuperGarbage binary file and how a loader works. After selecting the application to load, the loader requests the selected SuperGarbage binary file via input channel #1, word-by- word. The odd-numbered words contain the address where the following word will be stored. For example, in the figure below, 'Data 0' will be loaded into address 3 in your data memory. The loader continues loading data until it encounters the address -1 (0x3FFFFFFFF), which means the end of the file. The word following address -1 is the starting PC for the SuperGarbage program. After the loader is finished, it should call the VirtualMachine function you have written.

The following Java-esque pseudo-code shows how to load a program from the io_devices module and run the VirtualMachine. We have provided several SuperGarbage applications for you to test on. Changing the num_app variable in the pseudo-code will change which of these applications you load. You should write the loader in your assembly language, build the COE files, and generate a memory module. Be sure to include the assembly code for your loader in an appendix of your progress report.

// SuperGarbage Loader
// num _app
// 0: app0.bin
// 1: app1.bin
// 2: app2.bin

final int num_app = 0;

word mem[4096];
word startPC;

// basic code stub
set $SP;
set $GP;

// select an app
out( num_app, 1);

// load data from an external device while(addr != -1)
do {
    word addr, data;
    addr = in(0x1);
    data = in(0x1);
    
    if (addr == 0x3FFFFFFFFL) {
        startPC = data;
        break;
        
    } else {
        mem[addr] = data;
    }
} while(true);

// Finally, call the virtual machine
VirtualMachine(startPC, mem);

Step 6: VirtualMachine Test

You should now run your loaded with the app0 (Compare) to make sure your loader is working correct.

SuperGarbageSim

• load $file.bin
        loads *.bin file and *.in file, and set the $PC to the entry point of the application

• go $number
        executes next $number instructions. if $number is not specified, continues execution until a 'halt' instruction is executed.

• step
        execute one instruction at the current $PC, and increase $PC.

• get_pc
         prints the current $PC value

• set_pc $value
         sets the $PC to $value

• disasm $addr $size
         disassembles instructions from $addr to $addr + $size

• get_mem $addr $size
         prints data memory values from $addr to $addr + $size

• set_mem $addr $value
         sets the value at $addr of the memory with the value $value

• count
         shows the number of executed instructions

• help
         shows a help message

The following files comprise the SuperGarbage simulator. After downloading and compiling them, you can start the simulator by running the command 'java SuperGarbageSim'.

Step 7: Evaluation

Tips & Tricks

1. It is very painful to generate memory modules every time you modify your binary file. Fortunately, you do not have to generate a new memory module for behavioral simulations. The output Verilog file of the CORE Generator refers to a *.mif file for memory contents. Instead of generating new memory modules, you can simply modify your *.mif file, and perform the behavioral simulation again. It is highly recommended to generate *.mif files along with *.coe files from your simulator to make the debugging procedure much easier. The following MIF file is the MIF file for the 17-bit instruction memory you used in your fetch unit. It is similar to *.coe file, but uses a binary representation.

   
   	00000000000000000
   	00000000000000001
   	00000000000000010
   	00000000000000011
   	00000000000000100
   	00000000000000101
   	00000000000000110
   	00000000000000111
   	00000000000001000
   
   	 ...........