`timescale 1ns / 1ps
//
// CSE141L Lab 4, Part 2: Execution Unit Control and Test
// University of California, San Diego
// 
// Written by Donghwan Jeon, 5/21/2007
//
// Top test module
//
module top#(parameter D_WIDTH = 34, PA_WIDTH = 4)
(
	input  clk,
	input  reset
); 

wire read_req, write_req;
wire read_ack, write_ack;
wire [PA_WIDTH-1 : 0] read_addr;
wire [PA_WIDTH-1 : 0] write_addr;
wire [D_WIDTH-1 : 0] from_proc;
wire [D_WIDTH-1 : 0] to_proc;
   

core processor
(
	.clk(clk),
	.reset(reset),
    
	// I/O interface
	.in_req(read_req),
	.out_req(write_req),
	.in_addr(read_addr),
	.out_addr(write_addr),
	.in_data(to_proc),
	.out_data(from_proc),
	.in_ack(read_ack),
	.out_ack(write_ack)	 
); 


io_devices dev
(
	.clk(clk),
	.reset(reset),
	
	.read_req(read_req),
	.write_req(write_req),
	.read_addr(read_addr),
	.write_addr(write_addr),
	.dout(to_proc),
	.din(from_proc),
	.read_ack(read_ack),
	.write_ack(write_ack)	
);

endmodule