`timescale 1ns / 1ps
//
// CSE141L Lab 4, Part 2: Execution Unit Control and Test
// University of California, San Diego
// 
// Written by Donghwan Jeon, 5/18/2007
//

// Data Memory Module
//
// parameters:
// 	A_WIDTH: SRAM address width
// 	D_WIDTH: data width

module dmem#(parameter A_WIDTH = 13, D_WIDTH = 34)
(
   input  reset,
	input  clk,
	input  read_write_req,
	input  write_en,
	input  [A_WIDTH-1 : 0] addr,
	input  [D_WIDTH-1 : 0] din,
	output [D_WIDTH-1 : 0] dout,
	output refused
);

reg  [2:0] counter;
reg  refused_r;
reg  read_req_r;
reg  read_write_req_r;
wire refused_w;
wire [D_WIDTH-1 : 0] dout_temp;
wire write_control;


//assign write_control = read_write_req & write_en & ~refused_w;
assign write_control = read_write_req & write_en;
assign refused = refused_r & read_write_req_r;
//assign refused_w = counter[2] & counter[1] & counter[0];
assign refused_w = 0;
//assign dout = (refused | ~read_req_r)? {(D_WIDTH){1'b1}} : dout_temp;
assign dout = (~read_req_r)? {(D_WIDTH){1'b1}} : dout_temp;

dmem_34_8192 mem 
(
	.clka(clk),
	.dina(din), // Bus [33 : 0] 
	.addra(addr), // Bus [12 : 0] 
	.wea(write_control), // Bus [0 : 0] 
	.douta(dout_temp)
); // Bus [33 : 0] 

always@(posedge clk)
begin
 if (reset)
	counter <= 3'b0;
 else
	counter <= counter + 1;
 refused_r <= refused_w;
 read_write_req_r <= read_write_req;
 read_req_r <= read_write_req & ~write_en;
end	

endmodule