CSE141 Tutorial: Generating FIFO Module with Xilinx "CORE Generator"
Because you are changing the address width of your fetch unit, you will also need to update the FIFO. In our previous implementation, the data in each slot of the FIFO was 27 bits (17 for instruction and 10 for address) but it will need to change to 30 bits for your implementation. Please follow the steps below in order to correctly generate your new FIFO module.
- Launch the "CORE Generator" utility. You can find it at 'Start - All Programs - Xilinx ISE XYZ - Accessories - Core Generator' (where XYZ is the version of Xilinx ISE you are using).
- Choose 'Create new project'.
- Set 'Family' as 'Virtex4' and 'Device' as 'xc4vlx25'.
- Set 'Design Entry' to 'Verilog'.
- Choose 'FIFO Generator' and click 'customize'
- Type the component name you want to use, then click 'next'.
- Set 'Write Width' to 30 and 'Write Depth' to 16, meaning that you are generating a 30-bit width, 16 entry FIFO module.
- Check 'Valid Flag', and change 'Initialization' section to use 'Synchronous Reset'.
- Keep the default values for the next 2 screens ('Programmable Flags' and 'Data Count Options') then click finish on the following screen to generate your FIFO.
- After generating the FIFO module, you will find a few files in the project directory. Copy the *.v and *.ngc files to your Xilinx project directory and add them to the project as you did in lab 1. You will also need to update fifo.v to indicate that you are using the new fifo. For the usage of the generated module, refer to *.veo file.