Jingwei Lu's Homepage [resume]

email: francesco DOT ljw AT gmail DOT com




Biography

  • 06/2016 - Now: Principal Software Engineer @ Cadence Design Systems, Inc.
  • 01/2014 - 06/2016: Lead Software Engineer @ Cadence Design Systems, Inc.
  • 09/2010 - 12/2014: Ph.D. in Computer Science (Computer Engineering) @ University of California, San Diego
  •    -- Advisor: Prof. Chung-Kuan Cheng
       -- Thesis: Analytic VLSI Placement using Electrostatic Analogy
  • 02/2008 - 02/2010: M.Phil in Computer Engineering @ The Hong Kong Polytechnic University
  •    -- Advisor: Dr. Chiu-Wing Sham
       -- Thesis: Fundamental Research on Electronic Design Automation in VLSI Design - Routability
  • 10/2002 - 06/2006: B.S. in Information Engineering @ Zhejiang University
  •    -- Advisor: Kuang Wang


    Research

  • ePlace: Electrostatics based Placement
  • ePlace-MS: Electrostatics based Placement for Mixed-Size circuits
  • ePlace-3D: Electrostatics based Placement for 3D-ICs

  • Publications

    Please be aware that all papers are copyrighted by the organization responsible for the corresponding conference or journal.

    Conferences

  • J. Lu, H. Zhuang, I. Kang, P. Chen and C.-K. Cheng, "ePlace-3D: Electrostatics based Placement for 3D-ICs", ISPD 2016, pp. 11-18. (paper, slides).
  • X. Zhang, J. Lu, Y. Liu and C.-K. Cheng, "Worst-Case Noise Area Prediction of On-Chip Power Distribution Network", SLIP 2014, pp. 1-8. (paper, slides).
  • J. Lu, P. Chen, C.-C. Chang, L. Sha, D. J.-S. Huang, C.-C. Teng and C.-K. Cheng, "ePlace: Electrostatics Based Placement Using Nesterov's Method", DAC 2014, pp. 1-6. (nominated for best paper award, 12 out of 174 papers, 787 submissions) (paper, slides, poster).
  • J. Lu, P. Chen, C.-C. Chang, L. Sha, D. J.-S. Huang, C.-C. Teng and C.-K. Cheng, "FFTPL: An Analytic Placement Algorithm Using Fast Fourier Transform for Density Equalization", ASICON 2013, pp. 1-4. (paper, slides).
  • H. Zhuang, J. Lu, K. Samadi, Y. Du and C.-K. Cheng, "Performance-Driven Placement for Design of Rotation and Right Arithmetic Shifters in Monolithic 3D ICs", ICCCAS 2013, pp. 509-513. (paper, slides).
  • J. Lu and C.-W. Sham, "LMgr: A Low-Memory Global Router with Dynamic Topology Update and Bending-Aware Optimum Path Search", ISQED 2013, pp. 213-238 (best paper award, 3 out of 114 papers). (paper, slides).
  • S. K. Han, K. Jeong, A. B. Kahng and J. Lu, "Stability and Scalability in Global Routing", SLIP 2011, pp. 1-6. (paper, slides).
  • J. Lu, W.-K. Chow and C.-W. Sham, "Clock Network Synthesis with Concurrent Gate Insertion", PATMOS 2010, pp. 228-237. (paper, slides).
  • J. Lu, W.-K. Chow, C.-W. Sham and E. F. Y. Young, "A Dual-MST Approach for Clock Network Synthesis", ASPDAC 2010, pp. 467-473 (nominated for best paper award, 13 out of 115 papers, 340 submissions). (paper, slides).
  • Journals

  • J. Lu, H. Zhuang, P. Chen, H. Chang, C.-C. Chang, Y.-C. Wong, L. Sha, D. Huang, Y. Luo, C.-C. Teng and C.-K. Cheng, "ePlace-MS: Electrostatics based Placement for Mixed-Size Circuits", IEEE TCAD, 34(5) (2015), pp. 685-698. (paper).
  • J. Lu, P. Chen, C.-C. Chang, L. Sha, D. Huang, C.-C. Teng and C.-K. Cheng, "ePlace: Electrostatics based Placement using Fast Fourier Transform and Nesterov's Method", ACM TODAES, 20(2) (2015), article 17. (paper).
  • J. Lu, W.-K. Chow and C.-W. Sham, "Fast Power- and Slew-Aware Gated Clock Tree Synthesis", IEEE TVLSI, 20(11) (2012), pp. 2094-2103. (paper).
  • J. Lu, W.-K. Chow and C.-W. Sham, "A New Clock Network Synthesizer for Modern VLSI Designs", Integration, the VLSI Journal, 45(2) (2012), pp. 121-131 (Top 25 hotest ariticle in Integration, the VLSI journal of 2012). (paper).
  • C.-W. Sham, E. F. Y. Young and J. Lu, "Congestion Prediction in Early Stages of Physical Design", ACM TODAES, 14(1) (2009), (12:1-18). (paper).

  • Awards

  • 06/2014 - 06/2014: Nominated for best paper award at DAC-2014
  • 03/2013 - 03/2013: Best paper award at ISQED-2013
  • 09/2010 - 06/2013: Prestigious Jacobs fellowship at University of California, San Diego
  • 01/2010 - 01/2010: Nominated for best paper award at ASPDAC-2010
  • 03/2009 - 03/2009: 4th place at ISPD 2009 international clock network synthesis contest
  • 03/2008 - 02/2010: Research scholarship at The Hong Kong Polytechnic University
  • 06/2006 - 06/2006: Outstanding B.S. thesis at Zhejiang University
  • 10/2002 - 06/2006: Graduation from Chu Kochen Honors Program at Zhejiang University

  • Academic Services

  • 06/2014 - now: Reviewer of IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)
  • 08/2014 - now: Reviewer of IEEE Transactions on Very Large Scale Integration Systems (TVLSI)
  • 07/2015 - now: Reviewer of ACM Transactions on Design Automation of Electronic Systems (TODAES)
  • 06/2014 - now: Reviewer of Integration, the VLSI Journal
  • 08/2015 - now: Reviewer of Microelectronics Journal
  • 05/2016 - now: Reviewer of IEEE Transactions on Circuits and Systems II (TCAS-II)

  • Grad Coursework (selected)

  • CSE200 Computation and Complexity @ Spring, 2012
  • CSE221 Operating System @ Winter, 2012
  • CSE240A Computer Architecture @ Fall, 2011
  • CSE260 Parallel Computation @ Winter, 2012
  • CSE231 Advanced Compiler @ Spring, 2011

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