Homework and Lab Assignments

CSE 140

• Homework 1
• Homework 2
• Homework 3 Due Friday 2/27
• Homework 4 Due Friday

CSE 140L

• Lab Kit List
• OSCILLOSCOPE
• Oscilloscope Crib Sheet
• Tektronix Tutorial on oscilloscopes
• Another oscilloscope tutorial
• C.A.D.E.T. II Crib Sheet
• Lab 1
• Lab 2 - due Wed 2/18/98
• Lab 3 - due Mon 3/2/98

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CSE 140

Assignment 1 - Due Jan 23

• Problems found in Gajski, Principles of Digital Design

1. 3.7
2. 3.10
3. 4.6 - do as sum of products
4. 4.6 - do as product of sums

SOLUTION TO ASSIGNMENT 1 note corrections to 4.6a and 4.6b

CSE 140

Homework 2 - Due Feb 6

• Problems found in Gajski, Principles of Digital Design

1. Problem 4.8
2. Problem 4.10
3. Problem 4.19
4. Given a four-input Boolean function, f(a,b,c,d).


On set is F= sum m(0,3,7,11,13,15),
Don't care set is D= sum m(8,10).

a. Implement the function using an 8:1 multiplexer.
b. Implement the function using a minimal number of 4:1 multiplexers.
c. Implement the function using a minimal number of 2:1 multiplexers.
d. Implement the function using a 3:8 decoder and a minimal two level AND-OR network (sum of products).

Homework 2 Solutions, please note that these have not been checked by anyone else. If you think there is an error, please contact me immediately (cmautner@cs.ucsd.edu).

Homework 2 Points for each problem:

4.8 a) 6 b) 6 c) 6 d) 7

4.10 a) 10 b) 8 c) 7

4.19 hazardous design 5 hazard-free design 20

MUX, Dec problem a) 6 b) 6 c) 6 d) 7

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CSE 140L

Lab 1

• Assignment

Hints for Lab 1:

Assignment 5 iii:

• On some (or perhaps all) of the CADETs, the square wave generators do not have enough current sourcing capability to drive 6 TTL loads. Before looking for the spike on the power pin, make sure that all of the '04 outputs are clocking. If some are not, remove one inverter at a time until the remaining gates are all clocking.
• To see the spike on the power line you may have to set the o-scope input to AC-coupled and turn the voltage scale way down.

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CSE 140L

Lab 2 - due Wed 2/18/98

• Assignment

Modification to assignment: Draw item 3i in LogicWorks. You may use the clock symbol in place of the 555 circuit.

Useful Items

• Resistor Color Coding
• LM555 Timer Data Sheet (National) (requires Adobe Acrobat Reader)
• LM555 Timer Data Sheet (Signetics/Phillips) (requires Adobe Acrobat Reader)

Frequently Asked Questions

Q1: The lab calls for a 74163 but my kit has a 74161. What's the difference?
A1: The only difference between the '161 and the '163 is how the CLR pin works. Since for this experiment you will pull up the CLR input it doesn't matter which chip you have. (The CLR pin causes the counter outputs QA-QD to go to 0 at the same time. The '161 has an asynchronous CLR and the '163 is synchronous. Asynchronous means that the QA-QD outputs change to 0 immediately when the CLR input goes to 0; synchronous means that the QA-QD outputs change to 0 when the CLOCK input goes from 0 to 1 while the CLR input is 0.)

Q2: The professor said in class that pin 7 (ENPD) on the '163 is an output, but the Data Sheet shows it as an input.
A2: The Data Sheet is correct. The counter will not work unless ENPD is pulled up to a 1 (+5V).

Q3: How can I tell a 0.1uF capacitor from 0.01uF capacitor?
A3: In the kits from the bookstore, the (more) orange one that is labeled 103K is 0.01uF. (The way to read 103K is as "10" with three 0's after it or 10,000. This is the value in pF which translates to 0.01uF. The K (I think) is the accuracy.)

Q4: Why did the professor draw a 7401 (or 7400) NAND gate for one of the inverters of the ring oscillator.
A4: You only need the 7400 for the LogicWorks simulation. Without it LogicWorks will not start out in a known state. For the lab itself use inverters only.

Q5: The circuit description for the 555 is a little confusing, can you draw it, please?
A5: Sure

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Lab 3- due Mon 3/2/98

• Assignment

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CSE 140

Homework 3 - Due Friday 2/27

• Problems found in Gajski, Principles of Digital Design

1. 6.8
2. 6.10
3. 6.12
4. 6.16

• Solutions

Homework 4 - due Friday 3/13/98

1. Design a counter with output sequence 14, 15, 0, 7, 8, 9, 5, 6 in a wrap around fashion with a modulo­16 counter and a minimal number of 4:1 multiplexers.
2. A Full Subtracter inputs three bits: bit x, subtrahend y, borrow­in bit b_in, and outputs two bits: difference d, borrow­out bit b_out. Implement the Full Subtracter with a minimal two­level NAND gates.
3. Design a four­bit borrow­look­ahead subtracter with four Full Subtracters and a minimal network of AND, OR, NOT gates.
4. A serial subtracter inputs x_i, y_i, the i'th bit of two binary numbers in each clock cycle for i = 0 to n and outputs the difference. Implement the subtracter with a JK Flip­Flop and a minimal network of AND, OR, NOT gates.

Homework 4 Frequently Asked Questions

Q1: On problem 3 or 4, can we use XOR gates.
A1: No, just use AND, OR, NOT gates.

Q2: On problem 4 can we assume that we have the inverted terms (Q_D', Q_C', Q_B', Q_A') along with the regular ones (Q_D, Q_C, Q_B, Q_A)?
A2: Yes, you may.

Q3: I'm confused. In discussion section Craig said that to load a value into a counter, LOAD should be a 1 and CTEN (count enable) should be a 0. But the professor said in lecture that if LOAD is a 1, CTEN should be a X (don't care).
A3: The professor is correct.

Q4: I'm confused in one discussion section Craig said that states that are not part of a specified sequence should go to state 0, but in the next discussion he said that such states should never occur and so their transitions should be to don't care states.
A4: All states that are not part of a sequence should transition to don't care state.

Homework 4 Solutions