1. Design a counter with output sequence 14, 15, 0, 7, 8, 9, 5, 6 in a wrap around fashion with a modulo­16 counter and a minimal number of 4:1 multiplexers.

Current State						Next State
Q3	Q2	Q1	Q0		LOAD	Q3	Q2	Q1	Q0
0	0	0	0		1	0	1	1	1
0	0	0	1		X	X	X	X	X
0	0	1	0		X	X	X	X	X
0	0	1	1		X	X	X	X	X
0	1	0	0		X	X	X	X	X
0	1	0	1		0	X	X	X	X
0	1	1	0		1	1	1	1	0
0	1	1	1		0	X	X	X	X
1	0	0	0		0	X	X	X	X
1	0	0	1		1	0	1	0	1
1	0	1	0		X	X	X	X	X
1	0	1	1		X	X	X	X	X
1	1	0	0		X	X	X	X	X
1	1	0	1		X	X	X	X	X
1	1	1	0		0	X	X	X	X
1	1	1	1		0	X	X	X	X

2.A Full Subtracter inputs three bits: bit x, subtrahend y, borrow­in bit b_in, and outputs two bits: difference d, borrow­out bit b_out. Implement the Full Subtracter with a minimal two­level NAND gates.

x	y	bin		d	bout
0	0	0		0	0
0	0	1		1	1
0	1	0		1	1
0	1	1		0	1
1	0	0		1	0
1	0	1		0	0
1	1	0		0	0
1	1	1		1	1

3.Design a four­bit borrow­look­ahead subtracter with four Full Subtracters and a minimal network of AND, OR, NOT gates.

In general:

and

Let G_i = x_i'y_i and P_i = x_i' + y_i

then

solving for each b_i

b₁ = G₀ + P₀b₀

b₂ = G₁ + P₁b₁ = G₁ + P₁(G₀ + P₀b₀) = G₁ + P₁G₀ + P₁P₀b₀

b₃ = G₂ + P₂b₂ = G₂ + P₂(G₁ + P₁G₀ + P₁P₀b₀) = G₂ + P₂G₁ + P₂P₁G₀ + P₂P₁P₀b₀

b₄ = G₃ + P₃b₃ = G₃ + P₃(G₂ + P₂G₁ + P₂P₁G₀ + P₂P₁P₀b₀) = G₃ + P₃G₂ + P₃P₂G₁ + P₃P₂P₁G₀ + P₃P₂P₁P₀b₀

Finally, using the subtractors from problem 2:

4.A serial subtracter inputs xi, yi, the i'th bit of two binary numbers in each clock cycle for i = 0 to n and outputs the difference. Implement the subtracter with a JK Flip­Flop and a minimal network of AND, OR, NOT gates.

x	y	bin (Q)		d	bout (Qnext)	J	K
0	0	0		0	0	0	X
0	0	1		1	1	X	0
0	1	0		1	1	1	X
0	1	1		0	1	X	0
1	0	0		1	0	0	X
1	0	1		0	0	X	1
1	1	0		0	0	0	X
1	1	1		1	1	X	0