Names__________________ , __________________ , _________________
We learn about operation and internal design of various kinds of clocked flipflops.
1. Build a simple SR latch and deduce its state diagram.
2. See how a SR latch can alleviate the bouncing problem.
3. Add an enable line to the SR latch of lab 2 to make a transparent latch.
4. Connect two SR latches to make a master/slave flipflop.
5. Build an asynchronous ripple up counter.
6. Build a flashing display.
Construct the SR latch using a loop of twoNAND2 gates. The extra input of each NAND2 gate is connected to input signal S' and R', respectively.
i. Draw the circuit in TTL components and simulate the timing using LogicWorks.
ii. Draw a state diagram of the latch. Note that state 11 under input 11 leads to a race, i.e. the new state depends on which input arrives first. Since there are 2 state variables, the diagram contains four states. Use a splitting dashed arrow to demonstrate the race.
iii. Construct the hardware and compare the observed state diagram with the ideal one and explain the differences. In particular, which state that appears in the theoretical state diagram does not appear in the experiment?
A problem with the use of mechanical switches in digital circuits is a phenomenon known as "bouncing". Often when a switch is flipped from one terminal to another, it does not make a "clean" contact with the new terminal. Instead it will bounce off the terminal into the air several times before coming to rest. Because of this and the fact that TTL chips treat "floating" inputs as a logic 1, a single flip of a switch that should cause a 1to0 transition in fact causes many. This will often cause errors in the circuitry that is reading the switch.
We observe this phenomenon of switch bouncing and implement one solution to the problem. A single pole (one "lever") doublethrow (two output connections) switch has its two ends connect to two inputs S' and R' of SR latch with a pull up resistor (100 to 10K ohms) on each input. When wired in the configuration, the SR latch can solve the problem of switch bouncing. Hence this configuration is called a debouncing circuit. Build this debouncing circuit and use LEDs to check the outputs. In the next two lab sections, we verify that indeed every switch operation produces a single transition.
Demonstrate your circuit.___________________________ (signed by a TA)
Add an enable line to the SR latch of Lab 2 to build a transparent latch. Use 4 NAND2 gates to construct the latch.
i. Draw the logic diagram in TTL components using LogicWorks and simulate the timing of the circuit.
ii. Build the latch and use LEDs to check the outputs.
iii. Fill in the state table for the SR latch with inputs S, R and Enable.
Connect two SR latches in part 1 to make a master/slave flipflop. Use a debounced switch from part 2 for a clock input.
i. Draw the circuit in TTL components and simulate the timing using LogicWorks.
ii. Construct the hardware and check the outputs with LEDs.
iii. Draw a state diagram of the flipflop.
Build a 4bit asynchronous ripple up counter using 7474 FlipFlops. Measure the propagation delay through the counter from the rising edge of the clock to the rising edge output of each FlipFlop using an oscilloscope._____________________ (signed by a TA)
Design a circuit that lights a series of LED's in the following sequence forever:(0,1,2,3,4,5,6,7,0,1,...). Use 7474 FlipFlops and other gates as required. The sequence should be displayed on the upper leds of the 8 channel logic monitor on the CADET II. _______________ (signed by a TA)
1. Include a hard copy of the logic diagram and timing of 1.i. Show the state diagram in 1.ii. Explain the differences in 1.iii.
2. Include a hard copy of the logic diagram and timing of 3.i. Give the state table of 3.iii.
3. Include a hard copy of the logic diagram and timing of 4.i. Give the state diagram of 4.iii.
4. List the propagation delays in 5. Compare the results with the delays
derived from TTL Data Book.