CSE 140L Lab 1 - Combinational Circuit Design

Spring 2007, Professor Cheng, TAs Thomas Weng, Chengmo Yang, Yi Zhu

Due time: Demonstrate by 4/18 12:30PM, Report in class 4/18

Important! Please regularily check http://webboard.ucsd.edu for the latest updates and news regarding this lab. FAQs and announcements will be on the webboard, so check it often! Also, please get started sooner rather than later. This lab should take a bit more than 4 hours to do (assuming you understand the material), but since you must demonstrate this for us, you should be done before Wednesday.

Objective

- Learn and become familiar with the Altera Quartus II FPGA EDA tool.
- Learn how to design basic combinational digital components such as adders and multiplexers.
- Learn how to download designs onto the FPGA platform.
- Learn how to do functional and timing simulations and to examine the resulting waveforms.

Note, the first parts of this lab are almost entirely given to you in step by step instructions. The objective is for you to learn how to use Quartus II and the basic steps in designing a combinational circuit from specification to testing. That being the case, please make sure that you understand everything that you do in this lab!

Part 1. Introductory Tutorial

Follow along with the following tutorials, making sure that you understand each step. You will learn the basics of your hardware platform and the Quartus II EDA program. Tou will also learn how to design a very basic combinational circuit and simulate it on the actual FPGA board. If you do not understand a step, please ask a TA for help. Relevant chapters in the book are Chapters 2 and 3.

Software and Hardware Introduction
Basic Combinational Circuit Tutorial

Report:
- Write a short summary (max 100 words) of the overall process of using Quartus II to design a simple combinational circuit, and getting it to work correctly with your FPGA board.

Part 2. Spell U C S D on the Segment Display

In this part, you will design and run a circuit that will display U C S D on the board's segment display, depending on what button combination you have pressed. Follow along with the following tutorial to build and run your circuit. Note the processes that you do in order to design a circuit. Even though this part is mostly given to you, please make sure you understand each step.

U C S D Segment Display Tutorial

Report:
- Include schematic diagrams of your circuit
- Include your full truth table for UCSD. One row is given to you in the tutorial, provide the full truth table.
- Include the boolean expressions you derived from the truth table. Two were already given to you.

Part 3. Output 1-Bit Numbers with the Segment Display and Switch Input

In this part, you will learn to use the 8 switch input. You will design a combinational circuit that will display the number corresponding to the 1-bit value associated with switch 1. Thus, if input 1 is pressed down, then your segment display digit 2 should show 0, and if input 1 is in the up position, your segment display digit 2 will show 1.

After you have made your circuit, you will create a module for it in part 4, as you will use the 1-bit number displayer for your adder. Note, this means you will ignore inputs 2 through 8, and only focus on input 1 on your switch. This circuit is extremely easy to do and should take you no more than 30 minutes maximum. Don't forget to turn off all other segments!



Report:
- Include schematic diagrams of your circuit
- Include the truth table that you used to derive the appropriate outputs.
- In this part, you only worried about 1 input, so you only displayed 0 or 1 on the segment display. What if we had 3 inputs (and thus 3-bits)? Instead of just input 8, we used input 6,7, and 8. Then you would display 0 to 7 on the segment display, instead of just 0 or 1. Write out the truth table for this. (Hint, it is similar to what you did in part 2 to figure out the segment display for UCSD, except now you have 3 inputs instead of 2).

Part 4. Adders

In this part, you will design a full adder. You will learn how to create a module with a combinational circuit, and how to use that module in higher level circuits. By breaking up a combinational circuit into modules, you can begin to design more complicated circuits. You will use your 1-bit number displayer from part 3 to display the results on the segment display.

You will run your adder circuit on the FPGA board. The three inputs of the full adder, A, B and Cin, will be the switches 1, 2, 3 in the board; the output Cout will be displayed on digit 1 and S will be on digit 2. An included tutorial will help guide you, but by now you should know how to design a circuit and thus less detail will be given.

Adder Tutorial

Report:
- Include schematic diagrams of your circuit
- Include functional and timing diagrams of your simulation. (Enough to show that your adder works).
- What is the worst case delay through the adder? (That is, what path from an input to its destination output causes the longest delay in your circuit?)
- If we do not change the circuit but rearrange the inputs, say A becomes B, B becomes Cin, and Cin becomes A, will it still be a correct adder?

Part 5. Multiplexers

A 2-to-1 multiplexer (MUX) selects one of the two input signals according to the control signal:

Input: data signal A and B; control signal ctrl.

Output: signal C;

Function: C=A if ctrl=0; C=B if ctrl=1.

In this assignment, you are required to do the following tasks:

1. Build a 2-to-1 multiplexer using logic gates.

2. A 4-to-1 MUX selects one of the four input signals according to the control signal. Define the specification for this 4-to-1 MUX, i.e., input, output & their relationship.

3. Build the 4-to-1 MUX using the 2-to-1 MUX built in step 1. Demonstrate your work on the board. Use two push buttons as the control lines and switches 1-4 as inputs. Display 0/1 outputs on digit2. For example, if switch 1, 2 are 0 and 3, 4 are 1, then the display will show 0 if the push buttons are (0,0) or (0,1) and will show 1 for the other 2 combinations of button inputs.

Demonstration

You will need to demonstrate your project to a lab TA. Please look at the office hours for when we are available. Note, you can contact us if those times do not work, as we are happy to meet you outside those times too durning the evening. For your demonstration, you will need to demonstrate part 4 and 5. You can bring your laptop with your FPGA board to us and program the FPGA board in between demonstrations. So you will first program your board with Part 4, and demonstrate your working adder, and then reprogram it with your Part 5. For those of you without a laptop, we will try to set up machines in the lab that have Quartus II for your use, so you can bring your saved files on a flash drive or email and reprogram on the lab machines. If all looks good, we will give you thumbs up. If something doesn't work correctly, then please go back and fix it. You have up until 12:30 PM Wednesday 4/19 to demonstrate this to us.

Report Instructions

You lab report should include:

- Title page, which contains Names and PID of students, due date, title of lab, and brief discription of each person's contribution.
- Part 1 - answers
- Part 2 - schematic diagrams, answers
- Part 3 - schematic diagrams, answers
- Part 4 - schematic diagrams, functional diagrams, timing diagrams, and answers
- Part 5 - schematic diagrams, functional diagrams, timing diagrams, and answers

Grading

30% of your grade will be from the demonstration, so this is an easy 30%. Another 40% will be in your logic schematics and timing diagrams. Easy points assuming you were able to demonstrate this for us. 30% will be in your answers to the questions.

Final Notes

Good luck with your lab! Also please run through the interactive tutorial if you haven't before. Now that you have a good familiarity with the software and system, you can go through some of the guides with a better grasp than before. There are some other good software tutorials online as well, on the Altera Quartus II webpage. Being able to use EDA tools like Quartus II is important for this class. By now you should be able to:

1) Run Quartus II and open and create new projects.
2) Draw some logic design using the buttons and switches as inputs, and the segment display as outputs.
3) Create a module, and use that module in other schematic designs.
4) Download and test your design on your FPGA board.
5) Run simulations with your circuit and understand the functional and timing diagrams.