CSE 140L - Digital Systems Lab

Class

Wed 5:00pm - 6:20pm CSB 001

Course Description

This course covers topics in the design of digital circuits. The majority of the class is devoted to small digital design projects. This course also provides an introduction to hardware design tool called Xilinx Webpack and ModelSim.

Textbook

Not required. Professor recommend the following book:
"Digital Design: Principles & Practice", John F. Wakerly, Prentice Hall

Instructor

Isaac Chu, UCSD Guest Lecturer, Systems Architect
ichu@ece.ucsd.edu
Office hours: Wed after class @Roma (Price Center) & by appointment

Teaching Assistant

Raid Ayoub,  rayoub@cs.ucsd.edu
Office hours: EBU3B B270

Monday: 9:30-11:00 am + 5:00-700 pm

Friday: 9:30-11:00 am 

Additional Office hours for week 3, 5, 7, 10 (assignments due): Friday 5:30-8:30 pm

Jianhua Liu jhliu@cs.ucsd.edu
Office hours: EBU3B B270

Thursday 11:00-1:30

Additional Office hours for week 3, 5, 7, 10 (assignments due): Friday 11-2pm

 

Lab Assignments

Lab 1 (due week 3): gray-code enconder/decoder, 7-segment display
Lab 2 (due week 5): adder/subtractor, carry-lookahead adder and carry-select adder
Lab 3 (due week 7): state machine circuits (counter, traffic light controller)
Lab 4 (due week 10): introduction to CPU design (mini-CPU)

Course Plan

Week 1 : Introduction to digital designs, Xilinx design tools, 7-segment display
Week 2 : Hazards, gray-code encoder/decoder
Week 3 : Binary Arithmetics: Adder & subtractor
Week 4 : Carry-lookahead and Carry-select adder
Week 5 : Introduction to D-Flip Flop, Clock, and finite state machine.
Week 6 : Finite state machine circuits: counter, traffic light controllers
Week 7 : Mini-CPU concepts / machine code
Week 8 : CPU control unit
Week 9 : ALU
Week 10 : More advanced topics on digital designs
Final : June 12 Monday 7pm, CSB 001

Grading Policy

10% : Lab 1
15% : Lab 2
25% : Lab 3
30% : Lab 4
20% : Final Exam

Download

Webpack Download: Sorry, the files are too large. Please go to XILINX website to download the required tools. You'll need to download the free ModelSim. You will be asked to install the license for ModelSim in order to use it.

Other useful downloads:

·        Xilinx Webpack Tutorial - VHDL + ModelSim Simulation

·        A tutorial on using BUS in Xilinx ISE

·        A tutorial on creating simple finite state machine using VHDL

 

Announcements

·        5/31/06: No late turn-in accepted for lab 4

·        5/31/06: Bring a Blue book with you when you come to the final exam.

·        5/22/06:  Professor will not make it to his office hours this week.  If you need to meet with him this week, please email him to set up an appointment

·        For Lab 3, you are allowed to use VHDL ONLY for part 3. For part 1 & 2 you can use regular logic practice.

·        Points breakdown for lab 3 is available in Lab 3 link

·        A tutorial on creating simple finite state machine using VHDL is available in the download part.

·        The use of the BUS in Lab 2 is required.

·        In case that a Lab is done by more than one person, All people in the group need to be present during the demo. A deduction of 10% of the score would be applied to the person that is absent. 

·        Test cases guideline for Lab 2 is available in the lab link

·        A tutorial on using BUS in Xilinx ISE is posted

·        Notice: Version 6.1 of Xilinx Webpack is already installed in the machines at the lab EBU3B B270. Although it is a bit old, it is Ok to use it in case that you don’t have laptop

·        Office hours for the TA , Raid, are assigned

·        Office hours will start on the second week.