Introduction to Computer Architecture

CSE 141; Fall 2026

Processor Project · Week 5 of 11

Pipelined cpu_core

Released · Due

Draft: subject to change

This milestone is not final yet. Details, deliverables and grading may change before it is released.

Provided

Given to you

  • a few "more interesting", hazard-containing, programs

Not given

  • some other "more interesting", hazard-containing, programs :)

Due from you

Graded for correctness

  • Updated versions of programs to each have hazard-free and hazard-containing implementations.
  • Implementation of pipelined cpu_core.

Graded for feedback

  • Detailed block diagram for pipelined cpu_core.

Overview

Coming soon.

Goals
  • Structured approach to bigger, more complex open-ended Verilog / multi-module work
  • Demonstrate mastery of pipeline concepts.

Specification

Coming soon.

Getting Started

Coming soon.

Testing

Coming soon.

Submission & Grading

Coming soon.

Hints & FAQ

Coming soon.