Introduction to Computer Architecture
CSE 141; Fall 2026
Processor Project
ISA Scope
Your core grows to support more of the ARMv6-M instruction set as the quarter goes on. This table lists every ARMv6-M encoding and the week your core must first support it. Each week, and each level within week 3, adds to everything before it: once an encoding is in scope, it stays in scope.
Section numbers refer to the ARMv6-M Architecture Reference Manual. Where an instruction has several encodings, only the ones listed for a week are required that week. No week requires a deprecated feature (§D2.1).
Weeks after week 3 are a draft and may change before they are released.
| Instruction | Encoding | Section |
|---|---|---|
| Week 3 — Level 0: Move immediate | ||
| MOV (immediate) | T1 | A6.7.39 |
| NOP | T1 | A6.7.47 |
| Week 3 — Level 1: Register-register ALU | ||
| ADC (register) | T1 | A6.7.1 |
| ADD (register) | T1 | A6.7.3 |
| AND (register) | T1 | A6.7.7 |
| ASR (register) | T1 | A6.7.9 |
| BIC (register) | T1 | A6.7.11 |
| CMN (register) | T1 | A6.7.16 |
| CMP (register) | T1 | A6.7.18 |
| EOR (register) | T1 | A6.7.23 |
| LSL (register) | T1 | A6.7.36 |
| LSR (register) | T1 | A6.7.38 |
| MVN (register) | T1 | A6.7.45 |
| ORR (register) | T1 | A6.7.48 |
| ROR (register) | T1 | A6.7.54 |
| SBC (register) | T1 | A6.7.56 |
| SUB (register) | T1 | A6.7.66 |
| TST (register) | T1 | A6.7.71 |
| Week 3 — Level 2: Memory | ||
| LDR (immediate) | T1 | A6.7.26 |
| LDR (register) | T1 | A6.7.28 |
| LDRB (immediate) | T1 | A6.7.29 |
| LDRB (register) | T1 | A6.7.30 |
| LDRH (immediate) | T1 | A6.7.31 |
| LDRH (register) | T1 | A6.7.32 |
| LDRSB (register) | T1 | A6.7.33 |
| LDRSH (register) | T1 | A6.7.34 |
| STR (immediate) | T1 | A6.7.59 |
| STRB (immediate) | T1 | A6.7.61 |
| STRH (immediate) | T1 | A6.7.63 |
| Week 3 — Level 3: Remaining ALU | ||
| ADD (immediate) | T1 | A6.7.2 |
| ADD (immediate) | T2 | A6.7.2 |
| ASR (immediate) | T1 | A6.7.8 |
| CMP (immediate) | T1 | A6.7.17 |
| LSL (immediate) | T1 | A6.7.35 |
| LSR (immediate) | T1 | A6.7.37 |
| MOV (register) | T2 | A6.7.40 |
| REV | T1 | A6.7.51 |
| REV16 | T1 | A6.7.52 |
| REVSH | T1 | A6.7.53 |
| RSB (immediate) | T1 | A6.7.55 |
| SUB (immediate) | T1 | A6.7.65 |
| SUB (immediate) | T2 | A6.7.65 |
| SXTB | T1 | A6.7.69 |
| SXTH | T1 | A6.7.70 |
| UXTB | T1 | A6.7.73 |
| UXTH | T1 | A6.7.74 |
| Week 3 — Level 4: Branches | ||
| B | T1 | A6.7.10 |
| B | T2 | A6.7.10 |
| BL | T1 | A6.7.13 |
| BLX (register) | T1 | A6.7.14 |
| BX | T1 | A6.7.15 |
| Week 4 draft | ||
| No new instructions this week. | ||
| Week 5 draft | ||
| ADD (register) (r0–r12 only) | T2 | A6.7.3 |
| ADR | T1 | A6.7.6 |
| CMP (register) (r0–r12 only) | T2 | A6.7.18 |
| LDR (literal) | T1 | A6.7.27 |
| MOV (register) (r0–r12 only) | T1 | A6.7.40 |
| Week 6 draft | ||
| ISB | T1 | A6.7.24 |
| Week 7 draft | ||
| ADD (SP plus immediate) tentative | T1 | A6.7.4 |
| ADD (SP plus immediate) tentative | T2 | A6.7.4 |
| ADD (SP plus register) tentative | T1 | A6.7.5 |
| ADD (SP plus register) tentative | T2 | A6.7.5 |
| LDM, LDMIA, LDMFD tentative | T1 | A6.7.25 |
| LDR (immediate) tentative | T2 | A6.7.26 |
| POP tentative | T1 | A6.7.49 |
| PUSH tentative | T1 | A6.7.50 |
| STM, STMIA, STMEA tentative | T1 | A6.7.58 |
| STR (immediate) tentative | T2 | A6.7.59 |
| SUB (SP minus immediate) tentative | T1 | A6.7.67 |
| Week 8 draft | ||
| BKPT | T1 | A6.7.12 |
| CPS | T1 | A6.7.19 |
| MRS tentative | T1 | A6.7.42 |
| MSR (register) tentative | T1 | A6.7.43 |
| SVC | T1 | A6.7.68 |
| UDF | T1 | A6.7.72 |
| UDF tentative | T2 | A6.7.72 |
| WFE | T1 | A6.7.75 |
| WFI | T1 | A6.7.76 |
| YIELD | T1 | A6.7.77 |
| Week 9 draft | ||
| MUL | T1 | A6.7.44 |
| SEV tentative | T1 | A6.7.57 |
| Week 10 draft | ||
| DMB | T1 | A6.7.21 |
| DSB | T1 | A6.7.22 |
| Not required | ||
| STR (register) | T1 | A6.7.60 |
| STRB (register) | T1 | A6.7.62 |
| STRH (register) | T1 | A6.7.64 |