Agenda – CSE 141

Key dates for Fall Quarter 2026

Quarter Begins: Mon Sep 21
First Day of Classes: Thr Sep 24
Last Day of Classes: Fri Dec 4
Quarter Ends: Sat Dec 12
EGrades Deadline: Tue Dec 15

For our purposes, the week starts on Tuesday at 08:00 and ends on Monday at 20:00. Things that we provide/assign will be released Tuesday morning. Homework and project milestones are due Monday night. (Through week 2, weeks started on Monday at 08:00.)

		Lecture Topics	PrairieLearn Release: Tue 08:00 Due: Mon 20:00	Processor Project Release: Tue 08:00 Due: Mon 20:00
The Pivot	Week 0	Welcome & Intro [pptx] [pdf] Collect background / skills from roster. Adapt course to small population mode.
A minimal computer	Week 1	Machine Overview and Execution [pptx] [pdf] Building up from the middle out. ALU design and operation. Control/Data separation. Verilog Refresher [pptx] [pdf] What is (System) Verilog? Combinational vs. Sequential Some simple examples (adder, mux) Simulation vs. Synthesis ISA Design and ARM v6m [pptx] [pdf] What defines a machine? Design tradeoffs How does ARM v6m work?	Assigned: HW1 (short; releases Wed AM) Due: None.	`adder`
A minimal computer	Week 2	(Finish ISA Design Probably) Single-Cycle Machine [pptx] [pdf] [block diagram] Organization of components Single-cycle datapath Single-cycle control Live-Coding some Verilog [pptx] [pdf] [initial code] [final code] Example workflow Debugging and validation tools	Assigned: HW2 Due: HW1	`execute_unit`
Basic Pipelines	Week 3	Test 1 TTC Window: 10/12 – 10/16	This test covers all material up through this point. I.e., HW1 and HW2 content. The test will be administered at the TTC. You will have 20 minutes for this test.
	Week 3	Performance Analysis & Multi-Cycle Machines [pptx] [pdf] [block diagram] Defining performance Multi-Cycle Machines Amdahl's Law Refresher Pipelines [pptx] [pdf] [block diagram] Principles and performance Datapath Control in pipelines	Assigned: HW3 Due: HW2	Single-cycle `cpu_core`
	Week 4	Pipeline Details Hazards and Mitigations Data Hazards Control Hazards	Assigned: HW4 Due: HW3	Pipeline design & hazard analysis
Memory	Week 5	How Memory Works Hardware Peripherals and MMIO	Assigned: HW5 Due: HW4	Pipelined `cpu_core`
(Slack week)	Week 6	Test 2 TTC Window: 11/2 – 11/6	This test covers all material up through this point. I.e., HW1, HW2, HW3, HW4, and HW5 content. The test will be administered at the TTC. You will have 35 minutes for this test.
(Slack week)	Week 6	(No new conceptual material this week; slack week in the schedule; project deadlines may need to relax a little if we're pushing too hard and this is a window for catchup) Verilog Stuff (tbd/ideas) Fancier System Verilog Verification Synthesis and Timing Alternative tools	Due: HW5	AHB-Lite memory interface
Advanced Pipelines	Week 7	Exceptions and Interrupts Synchronous Exceptions Asynchronous Interrupts / HW Events (Maybe): SW-backed Virtual Timers (Maybe/If-Time) Branch Predictors	Assigned: HW6	Timer peripheral
Caches	Week 8	Caches Refresher / Introduction n.b., this should all be review, but seems like we're starting from blank on caches :/ Cache design and tradeoffs Cache performance	Assigned: HW7 Due: HW6	Exceptions
(Slack day & Holiday)	Week 9	Test 3 TTC Window: 11/20 – 11/30	This test covers all material up through this point. I.e., HW1, HW2, HW3, HW4, HW5, HW6, and HW7 content. The test will be administered at the TTC. You will have 45 minutes for this test.
(Slack day & Holiday)	Week 9	(No new conceptual material this week; slack week in the schedule; project deadlines may need to relax a little if we're pushing too hard and this is a window for catchup) TBD	Due: HW7	Cache design
Fancier Stuff	Week 10	Where do things go from here? Cortex M0+, M3, M4, M7, M23, M33... Cortex R? Applications core concepts	Assigned: HW8	Cache implementation
Finals Week	Week 11	Test 4 (Final Exam) TTC Window: 12/5 – 12/13	This test covers all course material. The test will be administered at the TTC. You will have 110 minutes for this test.
Finals Week	Week 11		Due: HW8	Final processor & report