Processor Project · Week 2 of 11

execute_unit

Released · Due

Provided

Given to you

  • top-level module definition for execute_unit
  • testbenches for most ALU operations

Not given

  • testbenches for missing ALU operations
  • buggy execute_unit that fails missing testbenches

Due from you

Graded for correctness

  • implementation for execute_unit
  • testbenches for missing ALU operations

Graded for feedback

Block Diagram

We recognize, and apologize, that the block diagram requirement was added late in the week. Our primary goal is to get your group to meet and start planning, and especially to agree on a division of labor for next week's milestone.

Draw a block diagram of the single-cycle cpu_core you will build in week 3. Your processor should handle every week 3 instruction in the ISA scope table.

Your diagram should resemble the single-cycle block diagram from lecture, but it won't be identical.

Aspire to make it detailed: ideally, label every signal with its name and width (e.g., alu_result[31:0]). It doesn't have to be complete or perfect, and a clear photo of a whiteboard sketch is fine this week. Next week you will revise it to match what you actually build.

The block diagram is graded for feedback: credit is for a good-faith attempt, and we'll return comments, not a score.

Also note which member of your group is responsible for each component, either as annotations on the diagram or in a separate README.

We strongly recommend that you have different people write the testbench and the implementation for a given module—everyone in your group should plan to write at least one testbench and one module.

Hints & FAQ

What should I use to draw the diagram?

Anything that produces a clear, legible diagram is fine, but this diagram is big: dozens of blocks and labeled buses, revised every few weeks. Pick a tool whose wires stay attached when you move blocks around.

General-purpose drawing tools such as Google Drawings, PowerPoint, or Keynote are fine for a quick sketch, but they get painful at this size.

This week, a clear photo of a whiteboard sketch is fine. If you use a drawing tool, though, you will revise this diagram next week, so keep the editable source file in your repository, not just an exported image.

Goals
  • Write "real" Verilog
  • Demonstrate mastery of execute concepts
  • Preliminary mastery of ISA concepts