Processor Project · Week 4 of 11

Pipeline design & hazard analysis

Released · Due

Draft: subject to change

This milestone is not final yet. Details, deliverables and grading may change before it is released.

Provided

Given to you

  • a few "more interesting", hazard-free, programs

Not given

  • some other "more interesting", hazard-free, programs :)

Due from you

Graded for correctness

  • Hazard analysis of your assembly programs from last week.

Graded for feedback

  • Detailed block diagram for pipelined cpu_core.

Overview

Coming soon.

Goals
  • Structured approach to bigger, more complex open-ended Verilog / multi-module work
  • Use software to help with pipeline hazard concepts early.

Specification

Coming soon.

Getting Started

Coming soon.

Testing

Coming soon.

Submission & Grading

Coming soon.

Hints & FAQ

Coming soon.