CSE 141L: Computer Architecture Lab

Lecture Slides | Labs | WebBoard | Basic Course Information

Announcements:

Awards:

Congratulations to everyone on finishing their processor. The following is a list of awards presented at the awards ceremony on the last day of class.

Award Team
Highest Frequency/Best Multicycle Performance Aaron Heiber and Virginia Tice
Best Overall Performance/ISA Master Brandon Beresini
Most Area Efficient Patrick Lai and Lee Shu
Most Unique Design/Fastest Instruction Commit Tony Ma and Brian Malihan
Most Optimized Function Calling James Whiteside
Most Optimized Loads/Stores (Multi-cycle) Daniel Schatzle and Matthew Davis
Most Advanced Decoding Scheme / Paradigm Shifting Designs Augy St. Clair and Shahin Mani
Most Reslient Team / Bug-finding Masters Derek Bulner and Jon Sebastian
Simplest/Most Elegant Backend Datapath Design Elias Tong and Kellen Steffen
Most Optimized For Stack Operations James Lintern
Xilinx Tools Master Henry Koren

Course Overview:

Welcome aboard the AwesomeCore Inc. team. As part of your term-long project, you will be working creating a custom microprocessor. We will give you the specifications for this new processor but you will be in charge of creating a custom ISA for it and seeing its design through synthesis onto an FPGA. Your job won't be easy. In order to keep up with the big boys at Advanced Nano Devices and Letni Inc., you are going to have to use all of your computer architecture knowledge to create a pipelined processor that has best-in-class performance. Luckily you will have access to the powerful Xilinx ISE design kit and a partner of your choosing.

We know you have the experience and dedication necessary to succeed and can't wait for you to help AwesomeCore become the market leader in microprocessor design. If you have any questions, please contact your project managers, Michael and Sat.

 AMD Quad-core Phenom Processor

Lecture Slides

Date Topic
Nov. 14 Week 7 Status Update (Lab 3B Preview)
Nov. 7 Week 6 Status Update (Lab 2B Review, Lab 3A Preview)
Oct. 24 Week 4 Status Update (Lab 3A Preview)
Oct. 17 Week 3 Status Update (Lab 2A Review, 2B Preview)
Oct. 10 Week 2 Status Update w/ Advanced Verilog Design
Oct. 3 Verilog Tutorial, Part 2
Sept. 26 Verilog Tutorial, Part 1

Labs

Lab Title Due Date
Final Processor Benchmarking and Final Write-up Dec. 5
3, Part B Execution Unit Control and Test Prelim: Nov. 21
Final: Dec. 3
3, Part A Execution Unit Datapath Nov. 14
2, Part B Processor Front-End - Fetch Control and Test Nov. 7
2, Part A Processor Front-End - Fetch Datapath Oct. 17
1 Tools of the Trade Oct. 8

Basic Course Information

Grading

There are three main components to your grade: project and class participation. They are weighted as follows: The project consists of several subparts (labs) that build upon one another. Because it is not possible to start a lab before completing the previous labs, deadlines will be strictly enforced.

Project Evaluation

Your progress for this project will be measured in two ways: For each demonstration, you will meet with Sat and Michael to explain your progress and to provide a live demonstration of the current status of your project. They will expect you to be able to intelligently discuss your design choices. For most of the labs, you will be working with a partner. Both partners are expected to contribute equally in all parts of the lab and demonstration. Each lab will also require a written progress report. This report will detail milestones on your project. We will provide specific questions that you should briefly answer in your progress report.

Ultimately, your grade for this course will be based on your ability to complete all parts of the project satisfactorily. There will be hard deadlines for each part of the progress, with no late submissions accepted. If, at the end of the project, you have met all the deadlines and have a processor meeting all the specifications, you should expect to receive an A. Missed deadlines as well as incorrect or incomplete functionality will negatively effect your project grade.

WebBoard Participation

AwesomeCore has implemented a state-of-the-art online help forum using WebBoard. The WebBoard is meant as a forum for quickly answering project questions. Your project managers, Sat and Michael, will answer all policy questions on the WebBoard but time constraints limit them from immediately answering all project related questions. As such, you will be expected to actively contribute to the webboard to ensure its success. Sat and/or Michael will eventually answer all unanswered questions (with the possible exception of diifficult, existential questions) but you should not rely on them for a speedy response. The development tools used for this project are somewhat brittle so your first avenue for help with using them should be the WebBoard.

Class Participation

At AwesomeCore Inc. we value our team-based atmosphere. Your active participation in class will help contribute to a vibrant lab atmosphere that will help everyone become more productive hardware engineers. You will be expected to show up to all class lectures and should actively participate. Good teamwork is also a critical component to project success. You should take the time to pick a good partner and make sure that you are share the work equally. If we see that one team member is doing all the work, then both members of the team will be penalized so be equitable in delegating tasks.

Regrade Policy

If you would like to challenge the grade you received for any portion of the project, you must abide by the following guidelines:
  1. You must submit a request in writing describing the issue with the grade.
  2. We reserve the right to regrade the entire assignment, so your grade can go up or down.
  3. You must submit a regrade request within 1 week of the day the assignments are returned.