CSE141L Lab 2, Part A: Processor Front-End - Fetch Datapath

Lab Overview:

Lab Deliverables:

• Demonstration: None
• Progress Report: Answer all the questions that are found in the lab description. There are 6 total questions but they are much more involved than the questions in lab 1. Please make your answers thorough but also succinct. Again, you will be submitting your report via e-mail to Sat.
• Files: You will need to submit all your Verilog (i.e. .v files). Create a zip file with all these files and e-mail them to Sat by the lab deadline.
  Important Note: In order to make sure none of your files are lost, you must follow these guidelines:
  1. All your Verilog files should have your name and student id in comments at the top.
  2. Your zip file should have the following naming convention: cse141L-lab2-part_a-lastname-firstname.zip. For example, Sat's zip file would have the following name: cse141L-lab2-part_a-Garcia-Sat.zip.
  3. Your progress report should be in PDF format and have the following naming convention: cse141L-lab2-part_a-lastname-firstname.pdf. For example, Sat's progress report would have the following name: cse141L-lab2-part_a-Garcia-Sat.pdf.
  4. The subject of your submission e-mail should be the following: [CSE141L] Lab 2, Part A Submission - Last Name, First Name. Again, as an example, Sat's would be: [CSE141L] Lab 2, Part A Submission - Garcia, Sat

Lab Description:

Lab Files:

Fetch Unit Specification

module fetch#(parameter I_WIDTH = 17, A_WIDTH = 10, O_WIDTH = 5)
(
	input	clk,

	// inputs from the exec unit
	input	dequeue,
	input	restart,
	input	[A_WIDTH-1 : 0]	restart_addr,

	// memory interface
	input	load_store_valid,
	input	store_en, 
	input	[A_WIDTH-1 : 0] load_store_addr,    
	input	[I_WIDTH-1 : 0]  store_data,        
	output	[I_WIDTH-1 : 0]  load_data,
	output	load_data_valid,

	// ouputs to the exec unit    
	output	[I_WIDTH-1 : 0]	instruction_data,
	output	[A_WIDTH-1 : 0]	instruction_addr,
	output	instruction_valid
);

1. An instruction contains 17 bits. The most significant bit (MSB) is the 'P' (or "prediction") bit. If the 'P' bit is set to '0' then the instruction is either: a) not a branch or b) is a branch that has been predicted as 'not taken.' The 5 least significant bits (LSBs) of the instruction are the 'offset' bits for branch instructions. We will use these 'offset' bits to calculate the branch target according to the following formula: target = PC + SignExt(offset). SignExt(offset) is simply the sign extended version of the offset. Note: The offset is given in 2's complement and therefore may contain a negative number. You do not have to worry about the other 11 bits of the instruction for this lab.
2. SRAM has 1024 (i.e. 1K) addresses and therefore uses 10 bits for addressing. Each address contains 17 bits of data. We have provided files for simulating (ram17_1024.v) and implementing (ram17_1024.ngc) the SRAM. The implementation of the SRAM was created using coregen, a utility from Xilinx, and is highly optimized. Please read the description of the file above to learn about what each address is initialized to in the SRAM.
3. The FIFO queue has 16 entries, each holding 27 bits of data. The entries of the FIFO are broken into two parts: 1) the address (10 bits) and 2) the instruction (17 bits). It is also a highly optimized implementation that was created by the coregen utility.
4. In order to allow the program counter (PC) to restart at an arbitrary address, 'restart' and 'restart_addr' are provided as inputs to the fetch unit. If 'restart' is set to '1' then the PC will change to the address specified by 'restart_addr' and the FIFO will be cleared. Using this mechanism, we can reset the fetch unit by setting 'restart' to '1' and setting 'restart_addr' to '0x0.' This will cause the fetch unit to start fetching instructions at address '0'.
5. To allow reading and writing to the SRAM, the fetch unit supports "load" and "store" instructions. Two inputs to the fetch unit, 'load_store_valid' and 'store_en', fully specify load and store instructions. When 'load_store_valid' is set to '1', the fetch unit know the instruction is a load or store. Setting 'store_en' to '1' further specifies the instruction as a store (conversely, a '0' value on 'store_en' implies a load). For load instructions, the fetch unit produces a 17-bit instruction on the 'load_data' output. In the case of a store, the fetch unit writes 'store_data' into the address specified by 'store_addr'.
6. Load and store instruuctions have a higher priority than other fetch unit operations, including restart. These memory operations receive higher priority because the processor back-end may be dependent on their timely execution.

Datapath Implemenation

The situation described in Q1 requires the use of an adder and MUX. Implement both of these components in Verilog in their respective files (adder.v and mux.v). Make sure you use RTL Verilog.

As mentioned earlier, the calculating the branch target requires the sign extended version of the offset. Implement the sign extension module in signext.v so that branches can function correctly. Hint: You can duplicate a bit N times by {N{1'bx}} in verilog. For example, 5'b11111 can be briefly expressed by {5{1'b1}}. )

You should now be ready to implement your fetch unit in Verilog (fetch.v). In doing so, you should follow these simple guidelines:

1. Use structural verilog, not a behavioral verilog or RTL verilog. You should instantiate mux, adder, and signext modules in the fetch.v file. The FIFO and RAM have already been instantiated in fetch.v for you..
2. Use non-blocking assignments (i.e. <=) for flip-flops.
3. Where applicable, always use signal names in the provided datapath schematic. Otherwise, use consistent and readable naming style. The naming convention, proper indentation, and style will be graded. Make sure your Verilog file is readable in the Xilinx ISE editor.
4. Your Verilog modules should be both synthesizable and implementable in Xilinx ISE.

Good luck!