CSE 140L Digital Systems Lab |
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| Class |
Tue 5:00pm - 6:20pm, Ebu3b 2154
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| Course |
This course covers topics in the design of digital circuits. The majority of the class is devoted to small digital design projects. This course also provides an introduction to hardware design tool called Xilinx Webpack and ModelSim.
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| Textbook |
Not required.
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| Instructor |
Isaac Chu, UCSD Guest Lecturer, Systems Architect ichu@ece.ucsd.edu Office hours: @ Ebu3b #2106 (starts on 2nd week) TBD |
| T.A. |
Raid Ayoub rayoub@cs.ucsd.edu Office hours: @ @ EBU3B B220 Tuesday: 9:00 - 11:00 am + Wednesday: 4:00 - 6:30 pm + Thursday: (9:00 - 10:00 am & 4:00 - 5:30 pm) + Friday: 2:00 - 5:00 pm
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| Course Plan |
Week 1 : Introduction to digital design, Xilinx webpack tool, Timing Diagram, Delay, 7-Segment Display, Week 2 : Practical Matters of Circuits, Gray-code Encoder/Decoder, Hazards Week 3 : Binary arithmetics : Ripple Adder/subtractor, Carry-Lookahead Adder, Carry-Select Adder. Week 4 : More practical Matters of Circuits, Introduction to VHDL Week 5 : Finite State Machine Circuits : Registers, Count-down circuit Week 6 : More FSM Circuit: Traffic Light Controller, Vending Machine (VHDL) Week 7 : CPU design (datapath & control) Week 8 : CPU components using VHDL Week 9 : More VHDL examples & Final Review Week 10 : In class Final Exam |
| Grading |
5 % : Lab 1 Tutorial 1 15 % : Lab 2 Tutorial 2 25 % : Lab 3 Tutorial 3 30 % : Lab 4 25 % : Final Exam |
| Assignments |
Lab 1 (due week 3) : gray-code encoder/decoder, 7-segment display Lab 2 (due week 5) : adder/subtractor, carry-lookahead adder & carry-select adder Lab 3 (due week 7) : state machine circuits (counters, traffic light controlders) Lab 4 (due week 10) : introduction to CPU design (mini-CPU) |
Announcements:
12/05: All Lab 4 interviews should be done by Friday 12/07
11/07: Lab 3 (part2): The Y1 & Y2 output logic given in class was incorrect. The correct logic is : Y1 = (not X1) AND X2. Y2 = X1 AND (not X2)
11/05: TA Raid will be holding additional office hours for tomorrow, Tuesday, from 12:30 - 2: 30 pm
11/05: Part 3 of Lab 3 has been dropped
10/30: Due to campus closure, Lab 2 due date has been extended to Tuesday of week 6 (11/6)
10/30: Few changes in TA Raid office hours
10/17: The location of TA Raid office hours has changed into Lab B220 because the machines in this Lab have Xilinx installed in them
10/17: TA Raid office hours for this Thursday 10/18 only is changed into 5:30 - 8:00 pm
10/7: TA Raid office hours for Tuesday and Wednesday in this week are canceled since he will be attending a conference
10/7: TA Raid office hours are assigned