CSE 140 Syllabus

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Online Required Textbook: Digital Design by F. Vahid

Students are required to have an account in zyBooks and to complete assigned exercises prior to the beginning of classes. The following document explains how to sign into zyBooks. Use the zybook code: UCSDCSE140Summer2015 to subscribe.

It is very important that you use the SAME username for both TED and ZyBooks. Here are the instruction on how to change the subscription details Any of the students can update their own subscription details from within the ZyBook, simply click on the action menu in the top right corner and select 'Show subscription'. From there you may update your subscription information.

Recommended Textbookis:

• [Harris]: Digital Design and Computer Architecture by David Mooney Harris and Sarah L. Harris
• [Vahid]: Digital Design by Frank Vahid

Peer Instruction : Clickers

The course lectures will follow a Peer Instruction format, a teaching model which places stronger emphasis on classroom discussion and student interaction. As part of this, you will be assigned an iClicker, which you will need to register on TED. You will be expected to have completed the assigned reading and ready to discuss with your classmates. The iClicker can be purchased at the UCSD book store.

Course Policy

• Assignments should be submitted via TED.
• All zyBook activities will be graded based on CORRECTNESS. Multiple attempts will not be marked down as long as you get the right answer.
• All written homeworks must be done individually.
• No extensions will be given on assignments except for real medical emergency.
• To submit a regrade request use the Google form
• All regrade requests are due two days after grades are released.
• If more than 60% of the class fill out CAPE evaluations, lowest quiz score will be dropped.
• Grades will be assigned using the standard scale. Plusses and minuses will be given at the instructor's discretion.

Schedule

Date	Lecture	Topics	Required Zybook Weekly Activities	Recommended Readings
Week 1 Mon	1	Course Overview - The digital abstraction and basic logic gates [Slides]		[Harris] Chapter 1
Tue	2	Combinational Logic Specification and Realization: Truth tables, Boolean Algebra, Boolean Equations, Boolean Algebra Axioms - DeMorgan's, Consensus, Specifying Combinational Circuits: POS and SOP canonical forms, [Before Slides] [After Slides]	Finish Zybook activities in sections 1.8, 1.11 and 1.13 before Fri (07/03)@10pm	[ZyBook] 1.6-1.13, 2.4 [Harris] Chapter 2, Section 2.1-2.4
Wed	3	Simplifying Combinational Circuits: 2 variable K-maps Simplifying incompletely specified functions Optimizing Combinational Circuits: Logic minimization with multivariable K-maps [Before Slides] [After Slides]	Finish Zybook activities in sections 1.14, 1.16 before Fri (07/03)@10pm	[ZyBook] 1.14- 1.16 [Harris] Chapter 2, Section 2.4-2.7
Thu	4	K-Maps with multiple solutions (essential and non-essential prime implicants and implicates) K-map to product of sum minimization K-Maps in higher dimensions [Before Slides] [After Slides]	Finish Zybook activities in sections 2.2, 2.3 before Fri (07/03)@10pm	[ZyBook] 2.2, 2.3
Week 2 Mon	5	K-maps in higher dimensions Sequential Network Components: Bistable memory elements flip-flops (D) [Before Slides] [After Slides]	Finish Zybook activities in sections 3.1,3.2 before Fri(07/10)@10pm	[Harris] Chapter 3, Section 3.1, 3.2
Tue	6	Sequential Network Components: Latches and flip flops [Before Slides] [After Slides]	Finish Zybook activities in sections 3.4, 3.5 and 3.6 before Fri (07/10)@10pm	[Harris] Chapter 3, Section 3.3, 3.4.1, 3.4.2
Wed	7	Sequential Network Specification: Finite State Machines Sequential Network Implementation: Moore and Mealy Machines [Before Slides] [After Slides]	Finish Zybook activities in sections 3.10 and 3.11 before Fri (07/10)@10pm	[Harris] Chapter 3, Section 3.4
Thu	8	Sequential Network Specification: From circuit to FSM [Before Slides] [After Slides]	Finish Zybook activities in sections 3.7 and 3.8 before Fri (07/10)@10pm	[Harris] Chapter 3, Section 3.4
Week 3 Mon	9	Sequential Circuits (contd) [Before Slides] [After]	Finish Zybook activities in section 3.13 before Fri (07/17)@10pm	[Harris] Chapter 2 Section 2.8.2, other?
Tue	10	Sequential Network Timing Analysis [Before Slides] [After Slides]		[Harris] Chapter 2 Section 2.8.2, other?
Wed	11	Midterm review [After slides]	Finish Zybook activities in sections 2.7, 2.8 and 4.5 before Fri (07/17)@10pm	[Harris] Chapter 3, Section 3.5
Thu 07/16		Midterm 1
Week 4 Mon	12	Timing (contd) Standard Combinational Modules: Decoders [Before slides] [After slides]	Finish Zybook activities in sections 5.1, 5.2 and 5.3 before Fri (07/24)@10PM	[Vahid] Chapter 5
Tues	13	Standard Combinational Modules: Decoders and Encoders, Multiplexer, Demultiplxer [Before Slides] [After Slides]	Finish Zybook activities in section 5.5 before Fri (07/24)@10pm	[Vahid] Chapter 5
Wed	14	RTL Design: High Level State Machines and Processor Design RTL Design: From pseudocode to circuit [Before Slides] [After Slides]	Finish Zybook activities in sections 5.6 and 5.7 before Fri (07/24)@10pm	[Vahid] Chapter 5
Thu	15	RTL Design (contd) [Before Slides] [After Slides]
Week 5 Mon	16	Midterm 2 review 1(FSM, RTL Design, HLSMs and Timing) [Before Slides] [After Slides]
07/28, 12:30pm-1:50pm		Midterm 2
Wed	17	ALU and Processor Design [Before Slides] [After Slides]