Part I General Info
1. A tutorial on a simple pattern recognizer (Updated 5/5)
2. Slides for 5/4 discussion session
3. Slides for 5/11 discussion session on glitches
Part II Q and A
There are some installation issues that prevent the state machine wizard
from working correctly in StateCAD on the lab machines. If we work on
the lab machines, we need to compose the state diagram manually. Look
through the tool buttons located to the left of the design window. There
are buttons for adding a state, a transition, and a reset. Click on the
corresponding buttons when editing the state diagram.
On the lab machines, when generating VHDL codes from a state diagram,
StateCAD can successfully compile your state diagram. But when it generates
VHDL, it complains at the last step and not show any VHDL codes. The VHDL
codes, however, should already be generated and stored to a file, in spite of the
error message. The VHDL code is named after the state diagram file with a
different extension .vhd. (e.g., if the state diagram is named mealy.dia, the
VHDL code is mealy.vhd). We should be able to include the generated
VHDL file in the Xilinx project and do the rest of the lab without any problem.
We can view/edit the VHDL code in Xilinx ISE.
The purpose is to show that different state encodings leads to different circuit
implementation, and thus different hardware cost and performance of state
machines. State encoding provides another dimension of optimizations. By
default, the Xilinx synthesis tool uses one hot encodings for state machines
to optimize speed.
A glitch is an undesired output transition. It happens because of the transient
output changes between multiple input transitions. For more details, please
refer to the discussion session slides.
Mealy machines is more likely to have glitches, because its output depends
on the input, which may change at any time. Moore machines are less likely
to generate glitches, since the output only depends on the flip-flop outputs,
which may change at roughly the same time.