Schedule and Lectures

April 2nd, Introduction, Bill Lin
Brief introduction to Application Specific Processors and an outline of the main ideas behind the course (pdf)
Readings: none
April 4th, Embedded Processors, Tim Sherwood
Overview of the embedded processor architecture including a look at current and next generation ARM processors. (pdf)
Readings: none
April 9th, Verilog, Bill Lin
Lecture will be on an introduction to the Verilog HDL. See here. The first assignment can be found at here.
Readings: none yet
April 11th, Project Details and Continued Verilog, Bill Lin and Brad Calder
Project description will be handed out
More Verilog will be presented.
Readings: none yet
April 16th, Supporting Secure Communications, Brad Calder
The easiest example on which to show the potential benifiets of customization is by adding support for secure communication. Huge speed ups can be obtained by adding small amounts of bit manupulation hardware. This lecture dives into the issues and implementations of providing secure channels. (pdf)
Readings: "CryptoManiac: A Fast Flexible Architecture for Secure Communication", Lisa Wu, Chris Weaver, and Todd Austin
April 18th, SimpleScalar Tutorial, Brad Calder
An overview of simulation infrastructure to use for projects (pdf)
Readings: none yet
April 23th, System-on-Chip, Bill Lin
An introduction to Systems-on-chip design.
Part I (pdf) will focus on architecture issues. Part II (pdf) will focus on some CAD issues.
Readings: high-speed serial links (e.g. Raserlink); on-chip bus (e.g. AMBA, IBM's CoreConnect); reusable cores (e.g. Tality's collection); on-chip packet network (e.g. Dally's paper); embedded OS (e.g. Windriver).
April 25th, SoC Part 2, Bill Lin
See lecture material on April 23th on SoC.
Readings: See reading material on April 23th on SoC.
April 30th, Tensillica's XTensa Processor, Tim Sherwood
An overview of the work done at Tensillica on the XTensa customizable processor including both instruction level and co-processor level integration of customization. (pdf)
Readings: "XTENSA: A Configurable and Extensaible Processor", Ricardo Gonzales
May 2nd, Custom VLIW Embedded Processors, Brad Calder
Next generation embedded processors are going to be VLIW machines. This lecture will discuss some existing VLIW architectures targeted at the embedded market as well as the custom VLIW work at HP Labs Cambridge. (pdf)
Readings: none yet "Lx: A Technology Platform for Customizable VLIW Embedded Processing", Paolo Faraboschi, Geoffrey Brown, Joseph A. Fisher, Giuseppe Desoli, Fred (Mark Owen) Homewood
May 7th, From Software to Hardware Automatically, Tim Sherwood
Overview of several research systems that offer the promise of converting C code into Hardware in a fully automated fashion such as PICO, and Hall's the work from ISI. (pdf)
Readings: none yet "High-level Synthesis of Non-Programable Hardware Accelerator" Robert Schreiber Shail Aditya B.Ramakrishna Rau Vinod Kathail Scott Mahlke Santosh Abraham Greg Snider
May 9th, Imagine Processor (Media Processing with Streams), Brad Calder
(pdf)
Readings: Brucek Khailany, William J. Dally, Scott Rixner, Ujval J. Kapasi, Peter Mattson, Jin Namkoong, John D. Owens, Brian Towles, and Andrew Chang. Imagine: Media Processing with Streams. IEEE Micro, Mar/April 2001.
May 14th, Network Processors, Bill Lin
A discussion on the state of the art in network processor design including support for packet classification and intrusion detection. (pdf)
Readings: A subset of "Understanding Network Processors", Niraj Shah; Sample network processors: Broadcom/SiByte (e.g. BMC1250), PMC Sierra (e.g. RM9000x2), Intel IXP (e.g. IXP2800), MMC Networks, Cognigine, Xelerated.
May 16th, Design of Embedded Memories, Tim Sherwood
An intrduction to memory issues, including banking and partitioning, SRAM, mask and diffused ROM, DRAM, Flash, and different bus architectures. (pdf)
Readings: none
May 21st, Multiflow (Embedded Compilers, Part 1), Brad Calder
(pdf)
Readings: The Multiflow Trace Scheduling Compiler (1992), P. Geoffrey Lowney, Stefan M. Freudenberger, Thomas J. Karzes, W. D. Lichtenstein, Robert P. Nix, John S. O'Donnell, John C. Ruttenberg.
May 23rd, Embedded Compilers, Part 2, Brad Calder
(pdf)
Readings: Continue coverage of the Multiflow compiler, and we'll also be covering reconfigurable compilers.
May 28th, Protocol Offload Processing, Cluster Interconnects, Storage Networking, Bill Lin
(pdf)
Readings: none
May 30th, Programming Sensor Networks, Bill Lin
Readings: none
June 6th Application Accelerator Project Presentations
  • Florin - RFC (Network processing)
  • Tomas - MPEG2 decoder
  • Wei, Erez and Nathan - Susan (Image Processing)
  • Eugene - Rijndael kernel (Crypto)
  • Bryan - RSA encryption
June 7th Application Accelerator Project Presentations
  • Augustin, Eduardo and Ian - Huffman Encoder
  • Satish and Jeremy - Snort (Intrusion detection)
  • Suleyman and Jamison - ppmquant (Image Processing)
  • Floria and Zhengyong - LU decomposition

Travel for Brad Calder

May 14th and May 16th International Symposium on High Performance Computing
May 28th International Symposium on Computer Architecture

Travel for Bill Lin

April 4th Storage Networking World
May 7th and 9th Network/Interop