The nth Fibonacci number is the sum of the (n-1)th and (n-2)th Fibonacci number, and the first two numbers in the sequence are 1 and 1. So the Fibonacci sequence is:
The 23rd Fibonacci number is 46,368 (b520 in hex), which is the largest number you are required to generate. So the input is 5 bits wide (to accomodate the number 23), while the output is 16 bits wide (to accomodate 46,368). A list of the first 24 Fibonacci numbers is provided for you. The testbench that you write to test your design should have at least three different values of input_s and these should differ from each other by at least 4. Your timing diagram should show the testing of each of the three input_s values.
Note:Your fibonacci calculator must calculate
the nth fibonacci number. Using a ROM with stored fibonacci
numbers is not permitted.
Synthesis note: The loop limit for a for loop or a while loop cannot be variable. The loop limit must be constant.
Synthesis note:While in general, functions are synthesizable, recursive functions are not.
You should use this module declaration:
module fibonacci_calculator (input_s, reset, begin_fibo, clk, done, fibo_out) ;
input [4:0] input_s ;
input reset
;
input begin_fibo ;
input clk ;
output done ;
output [15:0] fibo_out ;
endmodule
If you use state machine design style 1, no registers will be synthesized in the combinational (unclocked) always block. You will need to instantiate the needed registers to hold the n-1 and n-2 fibonacci number to be included with your state machine in your fibonacci module. To use a single process to do the algorithm and synthesize the needed registers, you can use state machine design style 4, where signals assigned to in the clocked process are synthesized as registers. You can code the datapath operations in the state machine, which is called the functional rtl design style. An example is functional_rtl.v,
Signals, unless optimized out by the synthesis tool, that assigned to in an unclocked always block, will be synthesized as wires if no memory is inferred or as latches if memory is inferred. To avoid unwanted latches from the use of unclocked always blocks, signals assigned to in the unclocked process should be assigned a value for each branch in an if or case statement to avoid inferring memory. Signals, unless optimized out by the synthesis too, that are assigned to in a clocked always block, will be synthesized as registers.
The grading criteria for this project will be correctness. If the design performs correctly and you turn in the items listed below,
that is enough. For this project, criteria such as design area and delay will not be considered in the grading.
To complete this project, you should hand in: