// functional rtl style 
// One clocked process (always assignment block with event specification keyword posedge).

module functional_rtl (reset, clk, a, b, c, d, e, f, g);
   input reset;
   input clk;
   input [4:0] a;
   input [4:0] b;
   input [4:0] c;
   input [4:0] d;
   input [4:0] e;
   input [4:0] f;
   output [5:0] g;

   reg [5:0] g;            // Signals written to in an always block are declared as type reg.
   reg  state;             // Will synthesize to ffs only if the always block is sensitive to an edge, i.e. posedge clk.

   parameter  s0=0,        // Declare states using a parameter declaration. 
              s1=1,
              s2=2,
              s3=3;

   always @ (posedge clk or posedge reset)     // clocked process (always assignment block)
      if (reset)
         begin
            g <= 6'b000000;
            state <= s0;
         end
      else
         begin
	    case (state)        
	       s0: begin
		      g <= 6'b000000;      // Output g is registered.   
		      state <= s1;          // state is synthesized as the state register. 
		   end                     
	       s1: begin
		      g <= a + b;
		      state <= s2;
		   end 
	       s2: begin
		      g <= c + d;
		      state <= s3;
		   end 
	       s3: begin
		      g <= e + f;
		      state <= s0;
		   end 
	    endcase 
	 end      

endmodule