Verilog and CAD Tools Page
In this class, we will be using the following
:
Verilog: hardware description language
Synopsys: synthesis, area and timing analysis, technology mapping
Modelsim: functional simulation
0.13um TSMC CMOS: cell library
Volunteer course assistant for Verilog and CAD tools
:
John Bryan
Email:
jbryan@ucsd.edu
Lab hrs: Mon, Tue, Fri, 12:30-3:30pm, EBU-1 3327,3329
Resources
: click
here
for a list of resources.
Tutorial
: click
here
for a tutorial lab on Verilog and CAD tools.