CSE 140L - Digital
Systems Lab Fall 2006 |
|
Class |
Wed 6:30pm - 7:50pm CSB 001 |
Course Description |
This course covers topics in the design of
digital circuits. The majority of the class is devoted to small digital design
projects. This course also provides an introduction to hardware design tool
called Xilinx Webpack and ModelSim. |
Textbook |
Not required. Professor recommend the following book: |
Instructor |
Isaac Chu, UCSD Guest Lecturer, Systems
Architect
Wednesday: 5:00 pm - 6:30 pm |
Teaching Assistant |
Raid Ayoub, rayoub@cs.ucsd.edu
Tuesday: 4:00 pm – 6:00 pm
+ Thursday 4:00 pm – 6:00 pm
Friday:
10:00 am – 11:30 am + 6:00 pm-7:30pm
Office hours: @ EBU3B B270 Monday: 1:30 pm – 3:30 pm +
Friday: 9:00 am – 10:00 am + Friday 4:30 pm – 6:00 pm |
Lab Assignments |
Lab 1 (due week 3): Gray-code
enconder/decoder, 7-segment display |
Course Plan |
Week 1 : Introduction to digital designs, Xilinx design tools,
7-segment display |
Grading Policy |
10% : Lab 1 |
Download |
Webpack Download: Sorry, the files are too
large. Please go to XILINX website
to download the required tools. You'll need to download
the free ModelSim. You will be asked to install the license for
ModelSim in order to use it. · Xilinx Webpack Tutorial
- VHDL + ModelSim Simulation:
version v8.2i (latest)
version v8.1i (current version in
the Lab) · A tutorial on using BUS in Xilinx ISE · A tutorial on creating simple finite state machine using VHDLXilinx Webpack Tutorial - VHDL + ModelSim Simulation
(updated) |
11/26: Final exam will be given in class on 10th week Nov 29th at 630pm. Bring a blue
book. You may write any notes on the blue area.
11/26: You will be able to double check your lab scores on
the 10th week in class after you finish your exam.
11/26: Professor will
have office hours wed 4-6:15pm on the 10th week.
11/19: Professor will not be able to make it to his office hours on the
22nd. However, there still will be class at 630pm.
11/16: TA office hours for this Friday, 11/17, is changed to: 8:00-10:00
am + 5:00-7:30 pm.
11/6: TA office hours for Thursday,
11/09 have changed to 12pm - 2pm.
11/2: Test cases for Lab 3 are
available now in Lab 3 link.
11/1: Updated version of VHDL
tutorial is posted.
10/19: Test cases for Lab 2 are available now in Lab 2 link.
10/7: TA's friday office hours have changed.
Please check the updated schedule.
10/2: For (Lab 1: part 1) simplify
all variables but "D" in the 7-segment circuit.