CSE 140L - Digital Systems Lab

Fall 2006

Class

Wed 6:30pm - 7:50pm CSB 001

Course Description

This course covers topics in the design of digital circuits. The majority of the class is devoted to small digital design projects. This course also provides an introduction to hardware design tool called Xilinx Webpack and ModelSim.

Textbook

Not required. Professor recommend the following book:
"Digital Design: Principles & Practice", John F. Wakerly, Prentice Hall

Instructor

Isaac Chu, UCSD Guest Lecturer, Systems Architect
ichu@ece.ucsd.edu
Office hours: @
S&E library study room           

                     Wednesday: 5:00 pm - 6:30 pm

Teaching Assistant

Raid Ayoub,  rayoub@cs.ucsd.edu
Office hours: @ EBU3B B270

                    Tuesday: 4:00 pm – 6:00 pm + Thursday 4:00 pm – 6:00 pm

                    Friday: 10:00 am – 11:30 am + 6:00 pm-7:30pm


Sashikanth Madduri, smadduri@cs.ucsd.edu

Office hours: @ EBU3B B270

                    Monday: 1:30 pm – 3:30 pm +  

                    Friday: 9:00 am – 10:00 am + Friday 4:30 pm – 6:00 pm

 

Lab Assignments

Lab 1 (due week 3): Gray-code enconder/decoder, 7-segment display
Lab 2 (due week 5): Adder/subtractor, carry-lookahead adder and carry-select adder
Lab 3 (due week 7): state machine circuits (counter, traffic light controller)
Lab 4 (due week 10): Introduction to CPU design (mini-CPU)

Course Plan

Week 1 : Introduction to digital designs, Xilinx design tools, 7-segment display
Week 2 : Hazards, gray-code encoder/decoder
Week 3 : Binary Arithmetics: Adder & subtractor
Week 4 : Carry-lookahead and Carry-select adder
Week 5 : Introduction to D-Flip Flop, Clock, and finite state machine.
Week 6 : Finite state machine circuits: counter, traffic light controllers
Week 7 : Mini-CPU concepts / machine code
Week 8 : CPU control unit
Week 9 : ALU
Week 10 : Final Exam

Grading Policy

10% : Lab 1
15% : Lab 2
25% : Lab 3
30% : Lab 4
20% : Final Exam

Download

Webpack Download: Sorry, the files are too large. Please go to XILINX website  to  download  the required tools. You'll need to download the free ModelSim. You will be asked to install the license for ModelSim in order to use it.

Other useful downloads:

·    Xilinx Webpack Tutorial - VHDL + ModelSim Simulation:

           version v8.2i (latest)

           version v8.1i (current version in the Lab)

·     A tutorial on using BUS in Xilinx ISE

·     A tutorial on creating simple finite state machine using VHDLXilinx

 Webpack Tutorial - VHDL + ModelSim Simulation  (updated)

 

 


  

Announcements:

11/26: Final exam will be given in class on 10th week Nov 29th at 630pm Bring a blue book.  You may write any notes on the blue area.

11/26: You will be able to double check your lab scores on the 10th week in class after you finish your exam.

11/26: Professor will have office hours wed 4-6:15pm on the 10th week.

11/19: Professor will not be able to make it to his office hours on the 22nd.  However, there still will be class at 630pm.
11/16: TA office hours for this Friday, 11/17, is changed to: 8:00-10:00 am + 5:00-7:30 pm.

11/6: TA office hours for Thursday, 11/09 have changed to 12pm - 2pm.

11/5: The due date of (Lab 3) is extended to Monday, 11/13, due to Veteran’s Day holiday on Friday 11/10.

11/2: Lab 4 is posted.

11/2: Test cases for Lab 3 are available now in Lab 3 link.

11/1: Updated version of VHDL tutorial is posted.

10/25:  Lab 3 is posted.

10/19: Test cases for Lab 2 are available now in Lab 2 link.

10/19: In case that a Lab is done by more than one person, All people in the group need to be present during the demo. Points would be deducted from the person that is absent. The penalty of missing the demo in Lab 2 is (10% of Lab 2 points). This penalty will increase in Lab 3 to 20%, and in Lab 4 to 30%.   

10/7: TA's friday office hours have changed. Please check the updated schedule.

10/2: For (Lab 1: part 1) simplify all variables but "D" in the 7-segment circuit. 

10/1:  During ModelSim installation process, be sure to: (1) select the free version (2) select the Verilog as the default language when prompted (3) request license file (4) use license wizard to import license.

9/29:  We encourage you to start your labs early. Also it will be great if you can use your laptop, if you have one, since it is known from the past that the machines in the Lab sometimes don’t function properly.