|
Objectives
·
Total input bits for the CPU are 9-bit. ·
Total output for the CPU is 5-bits and one "Overflow
indicator" and one "Invalid Instruction Indicator". ·
5-bit addition with over flow. ·
Multiply by 2 with overlow (shift-left) and divide by 2
(shift-right). ·
A comparator (see below) ·
AND and OR functions. ·
Store the result value back to an input register. ·
It must have 2 5-bit registers that hold values to be used for
arithmetics. ·
It must have 1 5-bit register that hold ther result. ·
It takes in 9-bit value as input (4-bit instruction set &
5-bit data). ·
It output a 5-bit value as result of the calculations. ·
Each instruction will happen during one clock cycle. Detail Requirements: ·
0000 00000 - clear the two registers (output 0000). ·
0001 XXXXX - put XXXXX value into R1. ·
0010 XXXXX - put XXXXX value into R2. ·
0011 00000 - R2 = Rout value (write result back to R2). ·
0100 00000 - Rout = R1 + R2 with overflow indicator. ·
0101 00000 - Rout = R2 << 1 with overflow indicator. ·
0110 00000 - Rout = R2 >> 1. ·
0111 00000 - Rout = R1 & R2. ·
1000 00000 - Rout = R1 | R2. ·
1001 00000 - Comparator: If (R1 == R2) Rout =
"00000", else if (R1 > R2) Rout = "00001", else Rout =
"00010" ·
any other instruction value > 1001 will cause "Invalid
Instruction" flag to be 1. For Simulation, do the following steps: ·
Clear the two registers ·
Put value into register 1 ·
Put value into register 2 ·
Compare the two registers. ·
Add the 2 numbers together (should cause an overflow for at
least once in the simulation) ·
Take the previous result and put into register 2 ·
Multiply register 2 by 2 (should cause an overflow for at
least once in the simulation) ·
Divide register 2 by 2 ·
AND the values ·
OR the values ·
DO THIS THREE TIMES with 3 cases: (1) R1 == R2 (2) R1 > R2
(3) R1 < R2 Be sure your VHDL code can be synthesized!!! Grading: Show your code/circuit &
demonstrate your simulation result to the TA or professor at office hours
during week 10. |