I explore hardware and software techniques to increase reliability of memory and logic units. My research interests are in computer architecture, parallel processing, and compilers. The following is a list of my publications and patents.


Compiler Techniques to Reduce the Synchronization Overhead of GPU Redundant Multithreading

Manish Gupta, Daniel Lowell, John Kalamatianos, Steven Raasch, Vilas Sridharan, Dean Tullsen, Rajesh Gupta. In Design Automation Conference (DAC 2017) [ PPT | Talk ]

ASAR: Application-Specific Approximate Recovery to Mitigate Hardware Variability

Manish Gupta, Abbas Rahimi, Daniel Lowell, John Kalamatianos, Dean Tullsen, Rajesh Gupta. In Silicon Errors in Logic – System Effects (SELSE 2017) [ PPT | Talk ]

Reliability and Performance Trade-off Study of Heterogeneous Memories

Manish Gupta, David Roberts, Mitesh Meswani, Vilas Sridharan, Dean Tullsen, Rajesh Gupta. In International Symposium on Memory Systems (MEMSYS 2016) [ PPT | Talk ]

Verifying GPU Kernels by Test Amplification

Alan Leung, Manish Gupta, Yuvraj Agarwal, Rajesh Gupta, Ranjit Jhala, Sorin Lerner. In Programming Language Design and Implementation (PLDI 2012)


I have multiple patents which are waiting to be approved at United States Patent and Trademark Office (USPTO). The following is a selected list of my patents:

Programmable Paired Comparison-Store with Hardware Assist [Patent Pending]

Manish Gupta, Daniel Lowell

Bufferless Communication for Redundant Multithreading using Register Permutation [Patent Pending]

Manish Gupta, Daniel Lowell


Basic Data Structures & OO Design, Teaching Assistant, Fall 2015. [ Eval Section A00, Eval Section B00]

Software for Embedded Systems, Teaching Assistant, Spring 2014.


Email: manishg at cs dot ucsd dot edu
Office: 2150 EBU3b
Dept. of Computer Science and Engineering
University of California, San Diego
9450 Gilman Drive, Mail Code 0404
La Jolla, CA 92093-0404