Hardware and Embedded System Security

This primary research's goal is to come up with methods, tools, and models for building secure hardware. Our current research interest is hardware-security centric testing techniques to eliminate side-channels; computational side effects which unintentially leak information (e.g. the power the hardware consumes or the time it takes to perform its computation). Most of my research is focused on the latter case in which secret information can leak through the amount of time something takes to execute (for confidentiality) or untrusted computations can affect the response time of critical system components (for integrity). Currently, we are leveraging properties found at the gate-level (the lowest layer of digital abstraction) to accurately identify these timing-related information flows in order to implement mechanisms such that they are eliminated. This research ultimately provides strong guarantees that secret information will never leak in hardware or that critical components will always meet their response deadline.

A nice page of our broader hardware security work can be found here: Gate Level Information Flow Tracking

Selected Relevant Publications

[D&T '13] Eliminating Timing Information Flows in a Mix-trusted System-on-Chip
Jason Oberg, Timothy Sherwood, and Ryan Kastner
IEEE Design and Test of Computers, vol. 30, no. 2, March/April 2013

[DATE'13] A Practical Testing Framework for Isolating Hardware Timing Channels
Jason Oberg, Sarah Meiklejohn, Timothy Sherwood, and Ryan Kastner
The conference on Design Automation and Test in Europe (DATE 2013)

[DAC'11] Information Flow Isolation in I2C and USB
Jason Oberg, Wei Hu, Ali Irturk, Mohit Tiwari, Timothy Sherwood, and Ryan Kastner,
In Proceedings of the Design Automation Conference (DAC 2011)

[DAC'10] Theoretical Analysis of Gate Level Information Flow Tracking.
Jason Oberg, Wei Hu, Ali Irturk, Mohit Tiwari, Timothy Sherwood, and Ryan Kastner,
In the Proceedings of the Design Automation Conference (DAC 2010).