ECE260B/CSE241A Low Power VLSI Design Winter 2010

University of California, San Diego

Course Information

• Objective of this course is to investigate low power design techniques.

Instructor

• CK Cheng, CSE2130, ckcheng+200@ucsd.edu, 858 534-6184

Schedule

• Outlines
• Lectures: 5:00-6:20PM TTh, Center 216.
• Office hours: 10:30-11:30AM T, 11:00-12:00PM Th, CSE 2130.

Teaching Assistants

• Yulei Zhang, (10hrs/week) E-mail: y1zhang@ucsd.edu
• Amirali Shayan, (10hrs/week) E-mail: amirali@ucsd.edu
• Office Hours: weekly schedule
  

Textbook

• Low Power Design Essentials (Integrated Circuits and Systems), by Jan Rabaey, Springer, 2009.

Announcements

• 01/25: Please turn in the LAB1 report by emails to both of two TAs. One report per group is required. Late report is NOT accepted.
• 02/01: WebCT support is avaiable for the class, discussion about lab can be performed there.
• 02/02: Grades of LAB1 are posted on WebCT, log in WebCT to check your grades.
• 02/08: Deadline of Lab2 is extended to 02/12(Friday), please email your report to TAs by the end of that day.
• 02/12: Midterm review session is scheduled for Monday 02/15/10 from 12pm-1pm at CSE/EBU3 building room 1202. Midterm sample questions are posted in midterm section.
• 02/22: Midterm grades are posted on WebCT. Papers will be handed out on class. Midterm solutions are posted in the midterm section.
• 02/25: LAB3 is posted.
• 03/04: Final project is posted to the web.
• 03/10: Final project due date is extended to midnight 03/19/10.
• 04/01: Final project feedback for different groups is available here .

Lecture Notes

• Chapter 1: Introduction
• Talk of Moore, Paper, G.E. Moore, No exponential is forever: but "forever" can be delayed! ISSCC, 1.1, 2003.
• Paper, S. Rusu, et al., A 45nm 8-core enterprise Xeon processor ISSCC, pp. 56-57, 2009.
• Chapter 2: MOS Transistors
• Chapter 3: Power and Energy Basics
• Talk of Bohr, Paper, M. Bohr, The new era of scaling in an SoC world, ISSCC, pp. 23-28, 2009.
• Guest Lecture: Roadmap, A.B. Kahng.
• Chapter 4: Circuit Level Optimiation at Design Time
• Paper, F. Ishihara, et al., Level Conversion for Dual-Supply Systems, Int. Symp. on Low Power Electronics and Design, pp. 164-167, 2003.
• Chapter 7: Memory Optimization at Design Time
• Talk of Itoh, Paper, K. Itoh, Adaptive Circuits for the 0.5-V Nanoscale CMOS Era, pp. 14-20, ISSCC 2009.
• Chapter 9: Memory Optimization at Standby
• Chapter 10: Circuit and System Optimization at Runtime
• Thesis, Shidhartha Das, Razor: A variability-tolerant design methodology for low-power and robust computing, 2009.
• S.L. Liu, Speeding up processing with approximation circuits, IEEE Computer Magazine, pp. 67-73, March 2004.
• Guest Lecture: SOC Design and Automation, M. Severson.
• Chapter 5: Architecture, Algorithm, and Systems
• Addition: Ling's Adder.
• Guest Lecture: Low Power Implementation: A System Perspective, S. Dobre.
• Chapter 6: Interconnect and Clocks
• Talk of Ling, Paper, L. Zhang, et al., Repeated On-Chip Interconnect Analaysis and Evaluation of Delay, Power, and Bandwidth under Different Design Goals, IEEE Int. Symp. on Quality Electronic Design, pp. 251-256, 2007.
• Talk, Y. Zhang, "Prediction of High-Performance On-Chip Global Interconnection," ACM/IEEE System Level Interconnect Prediction, pp. 61-68, 2009.
• Talk, Y. Zhu, et al., "Advancing Supercomputer Performance Through Interconnect Topology Synthesis," ACM/IEEE Int. Conf. on Computer-Aided Design, pp. 555-558, 2008.
• Talk, W. Zhang, et al. "On-Chip Power Network Optimization with Decoupling Capacitors and Controlled-ESRs," Asia and South Pacific Design Automation Conference, 2010.
• Q. Wu, et al., "Clock-Gating and Its Application to Low Power Design of Sequential Circuits," IEEE Trans on Circuits and Systems I, pp. 415-420, 2000.
• Chapter 11: Ultra-Low Power/Voltage Design
• A. Wang, et al., Sub-threshold Design for Ultra Low-Power Systems, Springer 2006.
• Talk by G. Taylor on Energy Efficient Circuit Design and the Future of Power Delivery, Keynote Speech, EPEP 2009

Assignment

• Assignment 1: Transistors and Gates , Example Slides
• Assignment 2: Flip-Flops and Memories
• Assignment 3: Function Blocks
• Final Project: Designing Low Power Function Block

Midterm

• Midterm review session: Monday 02/15/10 12pm-1pm at CSE/EBU3 building room 1202.
• Exercise questions
• Exercise Solutions

Lab Resources

• Hspice Tutorials: Tutorial 1 , Tutorial 2 , Tutorial 3 .
• Hspice Manuals and References: Hspice User Guide , Hspice Command Reference , CosmosScope Reference .

Grading

• Quizzes: 5%
• Midterm: 30% (T 2/16)
• Assignment 1: Transistors and Gates, 15% (T 1/26)
• Assignment 2: Flip-Flops and Memory, 15% (T 2/9)
• Assignment 3: Function Blocks, 15% (T 2/23)
• Final Project: 20% (T 3/16)