**Online Required Textbook: Digital Design by F. Vahid**

Students are required to have an account in zyBooks and to complete assigned exercises at a due time.

It is important that you use the SAME username for both TED and ZyBooks. Here are the instruction on how to change the subscription details Any of the students can update their own subscription details from within the ZyBook, simply click on the action menu in the top right corner and select 'Show subscription'. From there you may update your subscription information.

**Recommended Textbooks and References: (reserved at Library)**

**R1: Digital Design and Computer Architecture**by David Mooney Harris and Sarah L. Harris**R2: Digital Design with RTL Design, VHDL, and Verilog**by Frank Vahid**R3: (Part III of) Digital Systems and Hardware/Firmware Algorithms**by M.D. Ercegovac and T. Lang**R4: BSV by Example, R.S. Nikhil and K. Czeck, 2010 [ pdf file].**

- 20% zyBook weekly activities
- 15% Homeworks
- 9% Iclickers (3/4 in class participation).
- 27% Midterm One (T 5/2/17)
- 28% Midterm Two (Th 6/8/17)

- 1% Final (take home exam due 10PM, Th 6/15/17)

- All zyBook activities will be graded based on CORRECTNESS. Multiple attempts will not be marked down as long as you get the right answer.
- All written homeworks must be done individually.
- Software BSV (Bluespec System Verilog) will be used for homeworks.
- (Homework only) 10% loss of the maximum possible credit for each day after the deadline but no credit after the solution is posted (Usually within one day after the deadline).
- If more than 85% of the class fill out CAPE evaluations, lowest homework score will be dropped.

Week | Lecture | Homework | Required zyBook Weekly Activities | Recommended Readings |
---|---|---|---|---|

1 | Course Overview - The digital abstraction and basic logic gates. Lecture 1 [pptx file] [ pdf file] |
Homework1 due Monday 4/17/17@11:59pm solution tex | zyBook activities in Chapter 1 due Sunday 4/9/17@11:59pm | zyBook Chapter 1 |

Combinational Logic: 1. scope; 2. Boolean algebra; 3. switching functions, logic diagrams, truth table; 4. handy tools: DeMorgan's, consensus, Shannon's expansion; 5. combinational circuits: POS and SOP canonical forms. Lecture 2 [pptx file] [pdf file] |
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2 |
Combinational Circuits: Logic minimization with 2-, multivariable- K-maps.
Lecture 3 [pptx file] [pdf file] |
Homework2 due Monday 4/24/17@11:59pm solution tex | zyBook activities in Chapter 2 due Sunday 4/16/17@11:59pm | zyBook Chapter 2 |

3 |
K-Maps (essential and non-essential prime implicants and implicates)
K-map to product of sum minimization K-Maps in higher dimensions
Lecture 4 [pptx file] [pdf file] Lecture 5 [pptx file] [pdf file] |
zyBook activities in sections 3.1-3.4, and sections 4.1-4.3 due Sunday 4/23/17@11:59pm | zyBook Chapters 3 & 4 | |

4 | Universal set, XOR, NAND, NOR gates, and block diagram transfers
Lecture 6 [pptx file] [pdf file] |
Homework3 due Monday
5/1/17@11:59pm solution tex
For midterm 1 exam, practice midterm 1 and the first two questions of midterm 2 of previous quarters. [Midterm 1 Exam, Fall 2014] [Midterm 1 Solution, Fall 2014] [Midterm 1 Exam, Winter 2016] [Midterm 1 Solution, Winter 2016] [Midterm 2, Fall 2014] [Midterm 2 Exam, Winter 2016] [Midterm 2 Solution, Winter 2016] |
No zyBook assignment | |

5 | Sequential Networks: Introduction and memory components
Lecture 7 [pptx file] [pdf file] |
[Midterm 1 Solution, Spring 2017] | zyBook activities in sections 3.5-3.8 Sunday 5/7/17@11:59pm | zyBook Chapters 3 |

6 | Sequential Networks: Specification, analysis and implementation
Lecture 8 [pptx file] [pdf file] |
Homework4 due Monday 5/22/17@11:59pm solution tex | zyBook activities in sections 3.9-3.13 Sunday 5/14/17@11:59pm | zyBook Chapters 3 |

7 | Sequential Networks: Specification, analysis and implementation
Lecture 9 [pptx file] [pdf file] |
Homework5 due Monday 6/5/17@11:59pm solution tex | zyBook activities in sections 4.4-4.6 Sunday 5/21/17@11:59pm | zyBook Chapters 4 |

8 | Sequential Networks: Timing
Lecture 10 [pptx file] [pdf file] |
zyBook activities in sections 6.1-6.7 Sunday 5/28/17@11:59pm | zyBook Chapters 6 | |

Standard Combinational Modules: Decoders and Encoders
Lecture 11 [pptx file] [pdf file] |
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9 | Standard Combinational Modules: Multiplexers and Demultiplexers
Lecture 12 [pptx file] [pdf file] |
[Midterm 2 Review pptx] | zyBook activities in sections 7.1-7.6 Sunday 6/4/17@11:59pm | zyBook Chapters 7 |

System Designs: Introduction and Implementation
Lecture 13 [pptx file] [pdf file] |
For midterm 2 exam, practice midterm 2 (F14, W16) after the first two
questions and midterm 3 (F14, W16).
[Midterm 3 Exam, Fall 2014] [Midterm 3 Solution, Fall 2014] [Midterm 3 Exam, Winter 2016] [Midterm 3 Solution, Winter 2016] |
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10 | System Designs: Implementation
Lecture 14 [pptx file] [pdf file] |
[Midterm 2 Solution, Spring 2017] | No new zyBook activities for the rest of quarter | |

Final |
Final Exam [pdf file] and a reference paper on retiming, [pdf file]. |
solution |