| Date | Lecture | Topics | Lecture Slides | Readings |
|---|---|---|---|---|
| Mon 03/30 | 0 | Course Overview, ISA |
[L0_M0330] | Chapter 1 |
| 1 - 3 | Instruction Set Architecture: MIPS (Arithmetic Logical, Control and Memory Operations) [MIPS Reference (Green Sheet)] |
[L1_W0401]
[L1_annotated]
[L2_F0403] [L2_annotated] [L3_M0406] [L3_annotated] |
RQ1: Sections 1.3, 2.1-2.3, 2.5 RQ1: Sections 2.6 - 2.10 [Hung Wei Tseng slides 20-26] [Hung Wei Tseng's slides 7-18] | |
| 4 - 5 | Measuring and Discussing Performance: The performance equation, Amdahl's Law and Benchmarking
|
[L4_W0408]
[L4_annotated] [L5_F0410] [L5_annotated] |
RQ2:Sections 1.6-1.10 [Michael Taylor's slides on Performance] [Hung-Wei Tseng's slides 5-25] [Hung Wei Tseng's slides 6-17] |
|
| 6 - 9 | ALU and Single Cycle Processor: Datapath and Controlpath design |
[L6_M0413]
[L6_annotated] [L7_W0415] [L7_annotated] [L8_F0417] [L8_annotated] [L9_W0422] [L9_annotated] |
RQ3:Sections 3.1, 3.2, 4.1 RQ4:Sections Appendix B.5, Section 3.5 RQ5:Sections 4.2-4.4 [Hung Wei Tseng's slides 7-21] |
|
| Fri 05/01 | Midterm 1 |
|||
| 10 - 11 | Pipelining Basics |
[L10_F0424]
[L10_annotated] [L11_M0427] [L11_annotated] |
RQ6(due Wed 5/6 @1pm): Sections 4.5-4.6 [Hung Wei Tseng's slides 4-23] |
|
| 12 - 20 | Data hazards, Control hazards, branch prediction |
[L12_W0429]
[L12_annotated] [L13_M0504] [L13_annotated] [L14_M0506] |
RQ7(due Fri 5/8 @1pm): Section 4.7 RQ8(due Wed 5/13 @1pm): Section 4.8 [Hung Wei Tseng's slides 4-25] | |
| Fri 05/22 | Midterm 2 |
|||
| Mon 05/25 | Campus holiday: Memorial Day |
|||
| 21-24 | Caches and Memory systems |
RQ9: Sections 5.1-5.3 [Hung Wei Tseng's slides (Part 1)] [Hung Wei Tseng's slides (Part 2)] [Hung Wei Tseng's slides (Part 3)] |
||
| 25 - 26 | Virtual Memory |
RQ10: Section 5.4, 5.7-5.8 | ||
| 27 | Superscalars |
Sections 6.1-6.2 | ||
| Fri 06/05 | 28 | Final review |
||
| 06/11, Thu 11:30am - 2:30pm in CENTR 214 | Final Exam |
Last updated: Fri Feb 14 16:15:24 -0800 2014 [validate xhtml]